參數(shù)資料
型號(hào)： AD9717BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/80頁
文件大小： 0K
描述： IC DAC DUAL 14BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 86mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 125M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 40 of 80
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for
the AD9715, 11 for the AD9716, and 13 for the AD9717)
accompanied by a qualifying clock (DCLKIO). The I and Q
data are provided to the chip in an interleaved double data
rate (DDR) format. The maximum guaranteed data rate is
250 MSPS with a 125 MHz clock. The order of data pairing
and the sampling edge selection is user programmable using
the IFIRST and IRISING data control bits, resulting in four
possible timing diagrams. These are shown in Figure 89,
DCLKIO
ZA
B
C
D
E
F
G
H
I DATA
Z
B
D
F
Q DATA
Y
A
C
E
072
65-
047
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
DCLKIO
ZA
B
C
D
E
F
G
H
I DATA
Y
A
C
E
Q DATA
X
Z
B
D
072
65-
048
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
DCLKIO
ZA
B
C
D
E
F
G
H
I DATA
Z
B
D
F
Q DATA
A
C
E
G
07
265-
049
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
DCLKIO
ZA
B
C
D
E
F
G
H
I DATA
Y
A
C
E
Q DATA
Z
B
D
F
07265-
050
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in-window formed by the setup and hold times, tS
and tH. Refer to Table 2 for setup and hold times. A detailed
timing diagram is shown in Figure 93.
DCLKIO
07
26
5-
05
1
tS tH
DB[n:0]
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE
AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Table 2, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS data control bit.
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