參數(shù)資料
型號(hào): AD9772A-EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/40頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9772A
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
DAC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 160M
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時(shí)間: 11ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9772A
AD9772A
Rev. C | Page 34 of 40
36
34
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
U1
AD9772A
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DVDD
C8
0.1F
C7
0.1F
TP14
TP15
RED
BLK
I OU
T
A
OU
T
B
RE
F
L
O
C6
1F
C5
0.1F
AVDD
RED
TP16
BLK
TP17
WHT
TP5
WHT
TP6
RE
F
IO
FS
A
D
J
C4
0.1F
R10
1.91k
R6
50
TP11
SLEEP
WHT
REFLO
INT REF
A
B
1
2
3
JP4
EXT REF
AVDD
CLK–
CLK+
DIV0
DIV1
PLLLOCK
LPF
35
33
R5
VAL
C1
VAL
PLLVDD
NOTE:
SHIELD AROUND R5, C1
CONNECTED TO PLLVDD
c
C9
1F
C10
0.1F
CLKVDD
A
B
1
2
3
JP6
A
B
1
2
3
JP5
A
B
1
2
3
JP7
CLKVDD
RED
TP7
RESET
TP10
WHT
DB3
DB2
DB1
(L
S
B
)D
B
0
TP1
WHT
MOD0
c
A
B
1
2
3
JP11
H
L
H
L
A
B
1
2
3
JP10
DVDD
DGND
MOD1
TP2
WHT
C11
0.1F
C12
1F
DVDD
TP3
WHT
TP4
WHT
1
2
c
J1
TP28
WHT
c
NOTE:
LOCATE ALL DECOUPLING CAPACITORS (C5 TO C12) AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON THE BOTTOM SIGNAL LAYER.
JP8
EDGE
CLOCK
A
B
1
2
3
JP3
SE
DF
CLKVDD
R2
1k
c
R3
1k
C19
0.1F
A
B
1
2
3
JP2
T1
1
2
3
S
SE
P
6
4
c
JP1
DF
1
2
c
CLOCK
J3
WHT
TP12
A
B
1
2
3
JP9
DF
SE
R1
50
c
T2
3
2
1
S
P
4
6
R17
VAL
R16
VAL
1
2
J6
IOUT
R8
50
C3
10pF
IA
R9
OPT
IB
C2
10pF
R7
50
02
25
3-
0
61
Figure 61. Drafting Schematic of Evaluation Board (Continued)
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