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參數(shù)資料
| 型號： | AD9781BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BT 600MSPS LVDS 72LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 315mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 600M |
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AD9780/AD9781/AD9783
Data Sheet
Rev. B | Page 28 of 32
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
FS ADJ (Pin 54). A simplified block diagram of the reference
circuitry is shown in Figure 62. The recommended value for
the external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear function
of this resistor, a high precision resistor improves gain matching
to the internal matching specification of the devices. Internal
current mirrors provide a current-gain scaling, where I DAC or
Q DAC gain is a 10-bit word in the SPI port register. The default
value for the DAC gain registers gives a full-scale current output
(IFS) of approximately 20 mA, where IFS is equal to
IFS = (86.6 + (0.220 × DAC gain)) × 1000/R
CURRENT
SCALING
1.2V BAND GAP
I DAC GAIN
Q DAC GAIN
AD9783
I DAC
Q DAC
DAC FULL-SCALE
REFERENCE CURRENT
REFIO
FS ADJ
0.1F
10k
06936-
059
Figure 62. Reference Circuitry
06936-
060
35
30
25
20
15
10
5
I FS
(
mA)
0
256
512
768
1024
DAC GAIN CODE
Figure 63. IFS vs. DAC Gain Code
DAC TRANSFER FUNCTION
Each DAC output of the AD9780/AD9781/AD9783 drives two
complementary current outputs, IOUTP and IOUTN. IOUTP provides
a near IFS when all bits are high. For example,
DAC CODE = 2N 1
where N = 12/14/16 bits for AD9780/AD9781/AD9783
(respectively), while IOUTN provides no current.
The current output appearing at IOUTP and IOUTN is a function of
both the input code, and IFS and can be expressed as
IOUTP = (DAC DATA/2N) × IFS
(1)
IOUTN = ((2N 1) DAC DATA)/2N × IFS
(2)
where DAC DATA = 0 to 2N 1 (decimal representation).
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
should be connected to matching resistive loads (RLOAD) that are
tied to analog common (AVSS). The single-ended voltage
output appearing at the IOUTP and IOUTN pins is
VOUTP = IOUTP × RLOAD
(3)
VOUTN = IOUTN × RLOAD
(4)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
There are two distinct advantages to operating the AD9780/
AD9781/AD9783 differentially. First, differential operation
helps cancel common-mode error sources associated with IOUTP
and IOUTN, such as noise, distortion, and dc offsets. Second, the
differential code-dependent current and subsequent output
voltage (VDIFF) is twice the value of the single-ended voltage
output (VOUTP or VOUTN), providing 2× signal power to the load.
VDIFF = (IOUTP – IOUTN) × RLOAD
(5)
ANALOG MODES OF OPERATION
The AD9780/AD9781/AD9783 use a proprietary quad-switch
architecture that lowers the distortion of the DAC by eliminating a
code-dependent glitch that occurs with conventional dual-switch
architectures. This architecture eliminates the code-dependent
glitches, but creates a constant glitch at a rate of 2 × fDAC. For
communications systems and other applications requiring good
frequency domain performance from the DAC, this is seldom
problematic.
The quad-switch architecture also supports two additional
modes of operation: mix mode and return-to-zero mode. The
waveforms of these two modes are shown in Figure 64. In mix
mode, the output is inverted every other half clock cycle. This
effectively chops the DAC output at the sample rate. This chop-
ping has the effect of frequency shifting the sinc roll-off from dc
to fDAC. Additionally, there is a second subtle effect on the output
spectrum. The shifted spectrum is also shaped by a second sinc
function with a first null at 2 × fDAC. The reason for this shaping
is that the data is not continuously varying at twice the clock
rate, but is simply repeated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9781-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9781 DGTL-TO-ANLG CNVRTR - Bulk |
| AD9782 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing |
| AD9783 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs |
| AD9783BCPZ | 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9783BCPZRL | 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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