參數(shù)資料
型號: AD9781BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 31/32頁
文件大?。?/td> 0K
描述: IC DAC 14BT 600MSPS LVDS 72LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 315mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 72-LFCSP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 600M
AD9780/AD9781/AD9783
Data Sheet
Rev. B | Page 8 of 32
06936-
003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
17
D9P
18
D9N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
D8
P
D8N
D7
P
D7N
D6
P
D6N
DCO
P
DCO
N
DV
DD33
D
VSS
DCI
P
DCI
N
D5
P
D5N
D4
P
D4N
35
D3
P
36
D3N
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FS ADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
D0N
D0P
D1N
D1P
D2N
D2P
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
A
V
DD33
A
V
DD33
A
VSS
IOU
T1
P
IOU
T1
N
A
VSS
AUX
1
P
AUX
1N
A
VSS
AUX
2N
AUX
2
P
A
VSS
IOU
T2
N
IOU
T2
P
A
VSS
A
V
DD33
A
V
DD33
R
E
FIO
PIN 1
INDICATOR
AD9781
(TOP VIEW)
NOTES
1. NC = NO CONNECT
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 3. AD9781 Pin Configuration
Table 7. AD9781 Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 6
CVDD18
Clock Supply Voltage (1.8 V).
2, 5
CVSS
Clock Supply Return.
3, 4
CLKP, CLKN
Differential DAC Sampling Clock Input.
7, 28, 48
DVSS
Digital Common.
8, 47
DVDD18
Digital Supply Voltage (1.8 V).
9 to 24, 31 to 42
D13P, D13N to D0P, D0N
Data Inputs. D13 is the MSB, D0 is the LSB.
25, 26
DCOP, DCON
Differential Data Clock Output. Clock at the DAC sample rate.
27
DVDD33
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
29, 30
DCIP, DCIN
Differential Data Clock Input. Clock aligned with input data.
43 to 46
NC
No Connection. Leave these pins floating.
49
SDO
Serial Port Data Output.
50
SDIO
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
51
SCLK
Serial Port Clock Input.
52
CSB
Serial Port Chip Select (Active Low).
53
RESET
Chip Reset (Active High).
54
FS ADJ
Full-Scale Current Output Adjust.
55
REFIO
Analog Reference Input/Output (1.2 V Nominal).
56, 57, 71, 72
AVDD33
Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70
AVSS
Analog Common.
59
IOUT2P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
60
IOUT2N
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
62, 63
AUX2P, AUX2N
Differential Auxiliary DAC Current Output (Channel 2).
65, 66
AUX1N, AUX1P
Differential Auxiliary DAC Current Output (Channel 1).
68
IOUT1N
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
69
IOUT1P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad
N/A
The heat sink pad on the bottom of the package should be soldered to the PCB plane that
carries AVSS.
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