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參數(shù)資料
| 型號(hào)： | AD9859/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9859 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9859 Eval Brd BOM AD9859, AD9951-54 Eval Brd Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9859 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 400MHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
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AD9859
Rev. A | Page 19 of 24
SYSCLK
SYNC_CLK
I/O UPDATE
DATA IN
I/O BUFFERS
DATA IN
REGISTERS
A
B
A
B
DATA 1
DATA 2
DATA 3
DATA 0
DATA 1
DATA 2
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B.
03375-
007
Figure 20. I/O Synchronization Timing Diagram
Synchronizing Multiple AD9859s
The AD9859 allows easy synchronization of multiple AD9859s.
There are three modes of synchronization available to the user:
an automatic synchronization mode, a software controlled
manual synchronization mode, and a hardware controlled
manual synchronization mode. In all cases, when a user wants
to synchronize two or more devices, the following considera-
tions must be observed. First, all units must share a common
clock source. Trace lengths and path impedance of the clock
tree must be designed to keep the phase delay of the different
clock branches as closely matched as possible. Second, the I/O
UPDATE signal’s rising edge must be provided synchronously
to all devices in the system. Finally, regardless of the internal
synchronization method used, the DVDD_I/O supply should
be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master; the other device(s) is slaved to this master. When
configured in this mode, the slaves automatically synchronize
their internal clocks to the SYNC_CLK output signal of the
master device. To enter automatic synchronization mode, set
the slave device’s automatic synchronization bit (CFR1<23> = 1).
Connect the SYNC_IN input(s) to the master SYNC_CLK
output. The slave device continuously updates the phase
relationship of its SYNC_CLK until it is in phase with the
SYNC_IN input, which is the SYNC_CLK of the master device.
When attempting to synchronize devices running at SYSCLK
speeds beyond 250 MSPS, the high speed sync enhancement
enable bit should be set (CFR2<11> = 1).
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK
cycle (1/4 SYNC_CLK period). To activate the manual
synchronization mode, set the slave device’s software manual
synchronization bit (CFR1<22> = 1). The bit (CFR1<22>) is
cleared immediately. To advance the rising edge of the SYNC_CLK
multiple times, this bit needs to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN
input pin is configured such that it advances the rising edge of
the SYNC_CLK signal each time the device detects a rising edge
on the SYNC_IN pin. To put the device into hardware manual
synchronization mode, set the hardware manual synchronization
bit (CFR2<10> = 1). Unlike the software manual synchroniza-
tion bit, this bit does not self-clear. Once the hardware manual
synchronization mode is enabled, all rising edges detected on
the SYNC_IN input cause the device to advance the rising edge
of the SYNC_CLK by one SYSCLK cycle until this enable bit is
cleared (CFR2<10> = 0).
Using a Single Crystal to Drive Multiple AD9859 Clock
Inputs
The AD9859 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9859s. In order to drive multiple AD9859s with one crystal,
the CRYSTAL OUT pin of the AD9859 using the external crystal
should be connected to the REFCLK input of the other AD9859.
The CRYSTAL OUT pin is static until the CFR2<9> bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
With the AD9859, the instruction byte specifies read/write
operation and register address. Serial operations on the AD9859
occur only at the register level, not the byte level. For the
AD9859, the serial port controller recognizes the instruction
byte register address and automatically generates the proper
register byte address. In addition, the controller expects that all
bytes of that register will be accessed. It is a required that all
bytes of a register be accessed during serial I/O operations,
with one exception. The IOSYNC function can be used to
abort an I/O operation, thereby allowing less than all bytes
to be accessed.
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