
AD9882A
Rev. 0 | Page 5 of 40
AD9882AKSTZ
Parameter
Conditions
Temp
Test Level
Min
Typ
Max
Unit
POWER SUPPLY
VD Supply Voltage
Full
IV
3.15
3.3
3.45
V
VDD Supply Voltage
Full
IV
2.2
3.3
3.45
V
PVD Supply Voltage
Full
IV
3.15
3.3
3.45
V
25°C
V
237
mA
IDD Supply Current (Typical Pattern)1, 2 25°C
V
25
mA
IPVD Supply Current (Typical Pattern) 1 25°C
V
57
mA
Total Supply Current with HDCP
Full
IV
340
367
mA
ID Supply Current (Worst-Case Pattern)3 25°C
V
247
mA
IDD Supply Current
(Worst-Case Pattern)
2, 325°C
V
61
mA
IPVD Supply Current
25°C
V
57
mA
Total Supply Current with HDCP
(Worst-Case Pattern)
2, 3Full
IV
385
420
mA
Power-Down Supply Current (IPD)
Full
VI
30
35
mA
AC SPECIFICATIONS
Intrapair (+ to –) Differential Input
Skew (TDPS)
Full
IV
360
ps
Channel-to-Channel Differential
Input Skew (TCCS)
Full
IV
1
Clock Period
Low-to-High Transition Time
for Data (DLHT)
Output drive = high, CL = 10 pF
Full
IV
2.2
ns
Output drive = medium,
CL = 7 pF
Full
IV
2.5
ns
Output drive = low, CL = 5 pF
Full
IV
3.2
ns
Low-to-High Transition Time
for DATACK (DLHT)
Output drive = high, CL = 10 pF
Full
IV
1.0
ns
Output drive = medium,
CL = 7 pF
Full
IV
1.6
ns
Output drive = low, CL = 5 pF
Full
IV
2.1
ns
High-to-Low Transition Time
for Data (DHLT)
Output drive = high, CL = 10 pF
Full
IV
2.2
ns
Output drive = medium,
CL = 7 pF
Full
IV
1.9
ns
Output drive = low, CL = 5 pF
Full
IV
1.7
ns
High-to-Low Transition Time
for DATACK (DHLT)
Output drive = high,
CL = 10 pF
Full
IV
1.0
ns
Output drive = medium,
CL = 7 pF
Full
IV
1.0
ns
Output drive = low, CL = 5 pF
Full
IV
1.4
ns
Clock -to- Data Skew,
4 tSKEW
Full
IV
–0.5
+2.0
ns
Duty Cycle, DATACK
4
Full
IV
40
46
50
%
DATACK Frequency (FCIP)
Full
VI
25
112
MHz
1 The typical pattern contains a gray scale area. Output drive = high.
2 DATACK load = 10 pF, data load = 10 pF.
3 The worst-case pattern contains a black and white checkerboard pattern. Output drive = high.
4 Drive strength = 11.