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參數(shù)資料
| 型號(hào)： | AD9882AKSTZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE/DVI 100MHZ 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬，DVI |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9882A
Rev. 0 | Page 15 of 40
SYNC-ON-GREEN (SOG)
The sync-on-green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via Register 0x0F,
Bits 7 to 3. The sync-on-green input must be ac-coupled to the
green analog input through its own capacitor as shown in
Figure 5. The value of the capacitor must be 1 nF ±20%. If sync-
on-green is not used, this connection is not required and
SOGIN should be left unconnected. Note that the sync-on-
green signal is always negative polarity. See the Sync Processing
Engine section for further information.
05123-005
GAIN
SOGIN
1nF
RAIN
47nF
BAIN
47nF
Figure 5. Typical Clamp Configuration
CLOCK GENERATION
A phase-locked loop (PLL) is employed to generate the pixel
clock. The Hsync input provides a reference frequency for the
PLL. A voltage controlled oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (Registers 0x01 and 0x02) and phase com-
pared with the Hsync input. Any error is used to shift the VCO
frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 6). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter, and the stable pixel time becomes shorter as well.
05123-006
PIXEL CLOCK
INVALID SAMPLE TIMES
Figure 6. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the
AD9882A’s clock generation circuit to minimize jitter. As
indicated in Figure 7, the clock jitter of the AD9882A is less
than 6% of the total pixel time in all operating modes, making
negligible the reduction in the valid sampling time due to jitter.
10
8
6
4
2
0
25.1
31.5
36.0
40.0
50.0
56.2
65.0
75.0
78.7
85.5
94.5 108.0 135.0
05123-007
PIXEL CLOCK FREQUENCY (MHz)
P
IX
E
L
CLO
CK
J
ITTE
R
(p-p)
(%
)
Figure 7. Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in Figure 8. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table 10.
05123-008
CP
0.0082
F
CZ
0.082
F
RZ
2.74k
FILT
PVD
Figure 8. PLL Loop Filter Detail
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| AD9882KSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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