參數(shù)資料
型號: AD9958/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 16/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9958
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9958 Eval Brd BOM
標(biāo)準(zhǔn)包裝: 1
系列: AgileRF™
主要目的: 計時,直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9958
主要屬性: 10 位數(shù)模轉(zhuǎn)換器,32 位調(diào)節(jié)字寬
次要屬性: 500MHz 2 通道圖形用戶界面
已供物品: 板,線纜,軟件
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9958BCPZ-REEL7-ND - IC DDS DUAL 10BIT DAC 56LFCSP
AD9958BCPZ-ND - IC DDS DUAL 500MSPS DAC 56LFCSP
Data Sheet
AD9958
Rev. B | Page 23 of 44
Eight-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 10 (eight-level).
The AFP select bits (CFR[23:22]) are set to a nonzero value.
The RU/RD bits (FR1[11:10]) and the linear sweep enable bit
(CFR[14]) are disabled. Note that the AFP select bits of the
other channel not being used must be set to 00. Table 11 shows
the assignment of profile pins and channels.
For the condition in Table 11, the choice of channel word registers
is based on the 3-bit value presented to Profile Pins [P0:P2]. For
example, if PPC = X10 and [P0:P2] = 111, the contents of the
Channel Word 7 register of Channel 0 are presented to the output
Channel 0.
16-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 11 (16-level).
The AFP select bits (CFR[23:22]) are set to the desired modulation
type. The RU/RD bits (FR1[11:10]) and the linear sweep enable
bit (CFR[14]) are disabled. The AFP select bits of the other channel
not being used must be set to 00. Table 12 displays how the profile
pins and channels are assigned.
For the conditions in Table 12, the profile register chosen is
based on the 4-bit value presented to Profile Pins [P0:P3]. For
example, if PPC = X11 and [P0:P3] = 1110, the contents of the
Channel Word 14 register of Channel 1 is presented to the
output of Channel 1.
Two-Level Modulation Using Profile Pins for RU/RD
When the RU/RD bits = 01, Profile Pin P2 and Profile Pin P3
are available for RU/RD. Note that only a modulation level of
two is available in this mode. See Table 13 for available pin
assignments.
Eight-Level Modulation Using a Profile Pin for RU/RD
When the RU/RD bits = 10, Profile Pin P3 is available for
RU/RD. Note that only a modulation level of eight is available
in this mode. See Table 14 for available pin assignments.
Table 11. Profile Pin and Channel Assignments for Eight-Level Modulation (No RU/RD)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X10
CH0
X
Eight-level modulation on CH0, no RU/RD
X11
CH1
X
Eight-level modulation on CH1, no RU/RD
Table 12. Profile Pin and Channel Assignments for 16-Level Modulation (No RU/RD)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X10
CH0
16-level modulation on CH0, no RU/RD
X11
CH1
16-level modulation on CH1, no RU/RD
Table 13. Profile Pin and Channel Assignments for Two-Level Modulation (RU/RD Enabled)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
101
CH0
CH1
CH0 RU/RD
CH1 RU/RD
Two-level modulation on CH0 and CH1 with RU/RD
Table 14. Profile Pin and Channel Assignments for Eight-Level Modulation (RU/RD Enabled)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X10
CH0
CH0 RU/RD
Eight-level modulation on CH0 with RU/RD
X11
CH1
CH1 RU/RD
Eight-level modulation on CH1 with RU/RD
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