參數(shù)資料
型號(hào): AD9958/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 31/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9958
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9958 Eval Brd BOM
標(biāo)準(zhǔn)包裝: 1
系列: AgileRF™
主要目的: 計(jì)時(shí),直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9958
主要屬性: 10 位數(shù)模轉(zhuǎn)換器,32 位調(diào)節(jié)字寬
次要屬性: 500MHz 2 通道圖形用戶界面
已供物品: 板,線纜,軟件
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9958BCPZ-REEL7-ND - IC DDS DUAL 10BIT DAC 56LFCSP
AD9958BCPZ-ND - IC DDS DUAL 500MSPS DAC 56LFCSP
Data Sheet
AD9958
Rev. B | Page 37 of 44
Table 29. Channel Register Map
Register
Name
(Serial
Address)
Bit
Range
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Channel
Function
Register1
(CFR)
(0x03)
[23:16]
Amplitude freq. phase
(AFP) select[23:22]
Open[21:16]
0x00
[15:8]
Linear
sweep
no-dwell
Linear
sweep
enable
Load SRR at
I/O_UPDATE
Open[12:11]
Must be 0
DAC full-scale current
control[9:8]
0x03
[7:0]
Digital
power-
down
DAC
power-
down
Matched
pipe delays
active
Autoclear
sweep
accumulator
Clear sweep
accumulator
Autoclear
phase
accumulator
Clear phase
accumulator2
Sine
wave
output
enable
0x02
Channel
Frequency
Tuning
Word 01
(CFTW0)
(0x04)
[31:24]
Frequency Tuning Word 0[31:24]
0x00
[23:16]
Frequency Tuning Word 0[23:16]
N/A
[15:8]
Frequency Tuning Word 0[15:8]
N/A
[7:0]
Frequency Tuning Word 0[7:0]
N/A
Channel
Phase
Offset
Word 01
(CPOW0)
(0x05)
[15:8]
Open[15:14]
Phase Offset Word 0[13:8]
0x00
[7:0]
Phase Offset Word 0[7:0]
0x00
Amplitude
Control
Register
(ACR)
(0x06)
[23:16]
Amplitude Ramp Rate[23:16]
N/A
[15:8]
Increment/decrement
step size[15:14]
Open
Amplitude
multiplier
enable
Ramp-up/
ramp-down
enable
Load ARR at
I/O_UPDATE
Amplitude scale
factor[9:8]
0x00
[7:0]
Amplitude scale factor[7:0]
0x00
Linear
Sweep
Ramp
(LSRR)
(0x07)
[15:8]
Falling sweep ramp rate (FSRR)[15:8]
N/A
[7:0]
Rising sweep ramp rate (RSRR)[7:0]
N/A
LSR Rising
Delta
Word1
(RDW)
(0x08)
[31:24]
Rising delta word[31:24]
N/A
[23:16]
Rising delta word[23:16]
N/A
[15:8]
Rising delta word[15:8]
N/A
[7:0]
Rising delta word[7:0]
N/A
LSR Falling
Delta
Word1
(FDW)
(0x09)
[31:24]
Falling delta word[31:24]
N/A
[23:16]
Falling delta word[23:16]
N/A
[15:8]
Falling delta word[15:8]
N/A
[7:0]
Falling delta word[7:0]
N/A
1
There are two sets of channel registers and profile registers, one per channel. This is not shown in the Table 29 or Table 30 because the addresses of all channel
registers and profile registers are the same for each channel. Therefore, the channel enable bits (CSR[7:6]) determine if the channel registers and/or profile registers of
each channel are written to or not.
2
The clear phase accumulator bit (CFR[1]) is set to Logic 1 after a master reset. It self-clears or is set to Logic 0 when an I/O update is asserted.
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