參數(shù)資料
型號(hào): ADAU1382BCPZ-R7
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32
文件頁(yè)數(shù): 1/84頁(yè)
文件大?。?/td> 1193K
代理商: ADAU1382BCPZ-R7
Low Noise Stereo Codec with
Recording and Playback Processing
ADAU1382
FEATURES
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 Ω load)
Built-in sound engine for audio processing
Wind noise filter
Automatic level control (ALC)
5-band equalizer, including notch filter
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
modulation (PDM)
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Digital still cameras
Digital video cameras
GENERAL DESCRIPTION
The ADAU1382 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1382 ideal for battery-powered audio applications.
A configurable sound engine provides enhanced record and
playback processing to improve overall audio quality.
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1382 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
The serial control bus supports the I2C or SPI protocols, and
the serial audio bus is programmable for I2S, left-justified, right-
justified, or TDM mode. A programmable PLL supports flexible
clock generation for all standard rates and available master clocks
from 11 MHz to 20 MHz.
FUNCTIONAL BLOCK DIAGRAM
PGA
LEFT
ADC
RIGHT
ADC
LEFT
DAC
RIGHT
DAC
PGA
BEEP
PDN
MICBIAS
LMIC/LMICN/
MICD1
LMICP
RMIC/RMICN/
MICD2
RMICP
AOUTL
AOUTR
SPP
SPN
PLL
SOUND ENGINE
DECIMATION
FILTERS
WIND NOISE
NOTCH FILTER
EQUALIZER
DIGITAL VOLUME
CONTROL
AUTOMATIC LEVEL
CONTROL
OUTPUT
MIXER
M
CKI
REGULATOR
CM
IOV
D
DG
ND
DV
DDO
UT
AV
DD1
AG
ND
1
AV
DD2
AG
ND
2
SERIAL DATA
INPUT/OUTPUT PORTS
AD
C_S
DAT
A/
GP
IO1
BCL
K/
G
P
IO
2
L
R
CL
K/
G
P
IO
3
DA
C_S
DAT
A/
GP
IO0
I2C/SPI
CONTROL PORT
ADDR
0
/CD
AT
A
ADDR
1/
C
L
AT
CH
S
CL
/CCL
K
S
D
A/
CO
UT
ADAU1382
MICROPHONE
BIAS
08
42
7-
00
1
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
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