參數(shù)資料
型號(hào)： ADAU1382BCPZ-R7
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32
文件頁(yè)數(shù)： 54/84頁(yè)
文件大?。?/td> 1193K
代理商： ADAU1382BCPZ-R7
ADAU1382
Rev. 0 | Page 58 of 84
AUDIO CONVERTER CONFIGURATION
Register 16407 (0x4017), Converter Control 0
Bits[6:5], On-Chip DAC Data Selection in TDM Mode
These bits set the position of the DAC input channels on a TDM
stream. In TDM 4 mode, valid settings are first pair or second
pair. In TDM 8 mode, valid settings are first pair, second pair,
third pair, or fourth pair. These bits should be set in conjunction
with Register 16406 (0x4016), Serial Port Control 1, Bit 3, DAC
channel position in TDM, to select where the data should appear
in the TDM stream.
Figure 67, Figure 68, and Figure 69 show examples of different
TDM settings.
Bit 4, DAC Oversampling Ratio
This bit sets the oversampling ratio of the DAC relative to the
audio sample rate. The higher rate yields slightly better audio
quality but increases power consumption.
Bit 3, ADC Oversampling Ratio
This bit sets the oversampling ratio of the ADC relative to the
audio sample rate. The higher rate yields slightly better audio
quality but increases power consumption.
Bits[2:0], Converter Sampling Rate
These bits set the sampling rate of the audio ADCs and DACs
relative to the sound engine’s audio sample rate.
Table 42. Converter Control 0 Register
Bits
Description
Default
7
Reserved
[6:5]
On-chip DAC data selection in TDM mode
00
00: first pair
01: second pair
10: third pair
11: fourth pair
4
DAC oversampling ratio
0
0: 128
1: 64
3
ADC oversampling ratio
0
0: 128
1: 64
[2:0]
Converter sampling rate; the numbers in parentheses are example values for a base sample rate of 48 kHz
000
000: fS (48 kHz)
001: fS/6 (8 kHz)
010: fS/4 (12 kHz)
011: fS/3 (16 kHz)
100: fS/2 (24 kHz)
101: fS/1.5 (32 kHz)
110: fS × 2 (96 kHz)
111: reserved
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