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| 型號： | ADAU1382BCPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32 |
| 文件頁數(shù)： | 7/84頁 |
| 文件大小： | 1193K |
| 代理商： | ADAU1382BCPZ-R7 |
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ADAU1382
Rev. 0| Page 15 of 84
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
S
DA/
CO
UT
A
DDR0/
CDAT
A
AD
DR1/
C
L
A
T
C
H
IOV
D
DA
C_S
DAT
A/
G
P
IO
0
AD
C_S
DAT
A/
G
P
IO
1
BCL
K/
G
P
IO
2
LR
C
LK
/G
P
IO
3
MI
C
B
IA
S
BE
E
P
L
M
IC/
L
M
ICN/
M
ICD1
LM
IC
P
RM
ICP
RM
IC/
RM
ICN
/M
ICD2
AO
UT
L
AO
UT
R
PIN 1
INDICATOR
1
CM
2
PDN
3
AGND1
4
AVDD1
5
DVDDOUT
6
DGND
7
GPIO
8
SCL/CCLK
24 NC
23 AGND2
22 SPP
21 NC
20 SPN
19 AVDD2
18 MCKO
17 MCKI
9
1
0
1
2
1
3
1
4
1
5
1
6
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
TOP VIEW
(Not to Scale)
ADAU1382
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1382 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
08
42
7-
0
7
Figure 7. 32-Lead LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
CM
A_OUT
VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs and DACs.
The material of the capacitors is not critical. This pin can be used to bias external analog
circuits, as long as they are not drawing current from CM (for example, the noninverting
input of an op amp).
2
PDN
A_IN
Power-Down. Setting this pin to 0 powers down the chip. Resides in AVDD1 domain.
3
AGND1
PWR
Analog Ground.
4
AVDD1
PWR
Analog Power Supply. Should be equivalent to AVDD2.
5
DVDDOUT
PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to
DGND with a 100 nF capacitor.
6
DGND
PWR
Digital Ground.
7
GPIO
D_IO
Dedicated General-Purpose Input/Output.
8
SCL/CCLK
D_IN
I2C Clock/SPI Clock.
9
SDA/COUT
D_IO
I2C Data/SPI Data Output.
10
ADDR0/CDATA
D_IN
I2C Address 0/SPI Data Input.
11
ADDR1/CLATCH
D_IN
I2C Address 1/SPI Latch Signal.
12
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which sets the highest allowed input voltage for the digital input pins. The current draw of
this pin is variable because it is dependent on the loads of the digital outputs. IOVDD
should be decoupled to DGND with a 100 nF capacitor.
13
DAC_SDATA/GPIO0
D_IO
DAC Serial Input Data/General-Purpose Input and Output.
14
ADC_SDATA/GPIO1
D_IO
ADC Serial Output Data/General-Purpose Input and Output.
15
BCLK/GPIO2
D_IO
Serial Data Port Bit Clock/General-Purpose Input and Output.
16
LRCLK/GPIO3
D_IO
Serial Data Port Frame Clock/General-Purpose Input and Output.
17
MCKI
D_IN
Master Clock Input.
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