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| 型號(hào)： | ADAU1382BCPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32 |
| 文件頁數(shù)： | 19/84頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | ADAU1382BCPZ-R7 |
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ADAU1382
Rev. 0 | Page 26 of 84
CLOCK GENERATION AND MANAGEMENT
The ADAU1382 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock manage-
ment. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Sampling Rates section.
Case 1: PLL Is Bypassed
If the PLL is bypassed, the core clock is derived directly from
the master clock (MCLK) input. The rate of this clock must be
set properly in Register 16384 (0x4000), clock control, Bits[2:1],
input master clock frequency. When the PLL is bypassed,
supported external clock rates are 256 × fS, 512 × fS, 768 × fS,
and 1024 × fS, where fS is the base sampling rate. The core clock
of the chip is off until Register 16384 (0x4000), clock control,
Bit 0, core clock enable, is set to 1.
Case 2: PLL Is Used
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1382
can be started by setting Register 16384 (0x4000), clock control,
Bit 0, core clock enable, to 1.This bit enables the core clock to all
the internal functional blocks of the ADAU1382.
PLL Lock Acquisition
During the lock acquisition period, only Register 16384 (0x4000),
clock control, and Register 16386 (0x4002), PLL control, are
accessible through the control port. Reading from or writing to
any other address is prohibited until Register 16384 (0x4000),
clock control, Bit 0, core clock enable, and Register 16386 (0x4002),
PLL control, Bit 1, PLL lock, are set to 1.
Register 16386 (0x4002), PLL control, is a 48-bit register for which
all bits must be written with a single continuous write to the
control port.
The PLL lock time is dependent on the MCLK rate. Typical lock
times are provided in Table 11.
Table 11. PLL Lock Time
PLL Mode
MCLK Frequency
Lock Time (Typical)
Fractional
12 MHz
3.0 ms
Integer
12.288 MHz
2.96 ms
Fractional
13 MHz
2.4 ms
Fractional
14.4 MHz
2.4 ms
Fractional
19.2 MHz
2.98 ms
Fractional
19.68 MHz
2.98 ms
Fractional
19.8 MHz
2.98 ms
ENABLING DIGITAL POWER TO FUNCTIONAL
SUBSYSTEMS
To power subsystems in the device, they must be enabled using
Register 16512 (0x4080), Digital Power-Down 0, and Register
16513 (0x4081), Digital Power-Down 1. The exact settings depend
on the application. However, to proceed with the initialization
sequence and access the RAMs and registers of the ADAU1382,
Register 16512 (0x4080), Digital Power-Down 0, Bit 6, memory
controller, and Bit 0, sound engine, must be enabled.
SETTING UP THE SOUND ENGINE
After the PLL has locked, the ADAU1382 is in an operational
state, and the control port can be used to configure the sound
engine. For more information, see the Sound Engine section.
POWER REDUCTION MODES
Sections of the ADAU1382 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, and the PLL.
In addition, some functions can be set in the registers to operate
in power saving, normal, or enhanced performance operation.
See the respective portions of the General-Purpose Input/Outputs
section for more information.
Each digital filter of the ADCs and DACs can be set to a 64× or
128× (default) oversampling ratio. Setting the oversampling ratio
to 64× lowers power consumption with a minimal impact on
performance. See the Typical Performance Characteristics section
and the Typical Power Management Measurements section for
specifications and graphs of the filters.
Detailed information regarding individual power reduction control
registers can be found in the Control Register Map section of this
document.
Power-Down Pin (PDN)
The power-down pin provides a simple hardware-based method
for initiating low power mode without requiring access via the
control port. When the PDN pin is raised to the same potential as
AVDD1, the internal digital regulator is disabled and the device
ceases to function, with power consumption dropping to a very
low level. The common-mode voltage sinks, and all internal
memories and registers lose their contents. When the PDN pin is
lowered back to ground, the device reinitializes in its default state,
as described in the
section.
POWER-DOWN SEQUENCE
When powering down the device, the IOVDD, AVDD1, and
AVDD2 supplies should be disabled at the same time, if possible,
but only after the analog and speaker outputs have been muted. If
the supplies cannot be disabled simultaneously, the preferred
sequence is IOVDD first, AVDD2 second, and AVDD1 last.
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