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參數(shù)資料
| 型號： | ADAV4601BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | TV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADAV4601
Rev. B | Page 26 of 60
The ADAV4601 control port auto-increments the address of each
write even across the boundaries of the different RAMs and registers.
TARGET/SLEW RAM
The target/slew RAM is a bank of 64 RAM locations, each of
which can be set to autoramp from one value to a desired final
value in one of four modes.
When a program is loaded into the program RAM using one or
more locations in the slew RAM to access the internal coefficient
data, the target/slew RAM is used by the DSP. Typically, these
coefficients are used for volume controls or smooth cross-fading
effects, but they can also be used to update any value in the
parameter RAM. Each of the 64 locations in the slew RAM is
linked to a corresponding location in the target RAM. When a new
value is written to the target RAM using the control port, the
corresponding slew RAM location begins to ramp toward the
target. The value is updated once per audio frame (LRCLK period).
The target RAM is 34 bits wide. The lower 28 bits contain the target
data in 5.23 format for the linear and exponential (constant decibels
and RC) ramp types. For constant time ramping, the lower 28 bits
contain 16 bits in 2.14 format and 12 bits to set the current step.
The upper six bits are used to determine the type and speed of
the ramp envelope in all modes. The format of the data write for
the data write format for the constant time ramping.
In normal operation, write data to the target/slew RAM using
the safe load registers as described in the Safe Loading to
Parameter RAM and Target/Slew RAM section. A mute slew
RAM bit is included in the audio core control register to
simultaneously set all the slew RAM target values to 0. This is
useful for implementing a global multichannel mute. When this
bit is de-asserted, all slew RAM values return to their original
premuted states.
Table 12. Linear, Constant Decibels, and RC Ramp Data Write
Byte 0
Byte 1
Bytes[2:4]
000000,
Curve_Type[1:0]
Time_Const[3:0],
Data[27:24]
Data[23:0]
Table 13. Constant Time Ramp Data Write
Byte 0
Byte 1
Bytes[2:4]
000000,
Curve_Type[1:0]
Update_Step[0],
#_of_Steps[2:0], Data[15:12]
Data[11:0],
Reserved[11:0]
There are four types of ramping curves: linear, constant decibels,
RC, and constant time.
The linear ramping curve—The value slews to the target
value using a fixed step size.
The constant decibels ramping curve—The value slews to
the target value using the current value to calculate the step
size. The resulting curve has a constant rise and decay when
measured in decibels.
The RC ramping curve—The value slews to the target value
using the difference between the target and current values
to calculate the step size, resulting in a simple RC response.
The constant time ramping curve—The value slews to the
target value in a fixed number of steps in a linear fashion. The
control port mute has no effect on this type of ramping curve.
Table 14. Target/Slew RAM Ramp Type Settings
Settings
Ramp Type
00
Linear
01
Constant decibels
10
RC
11
Constant time
The following sections detail how the control port writes to the
target/slew RAM to control the time constant and ramp type
parameters.
Ramp Types[1:3]—Linear, Constant Decibels, and RC
(34-Bit Write)
The target word for the first three ramp types is broken into
three parts. The 34-bit command is written with six leading 0s
to extend the data write to five bytes. The parts of the target
RAM write are
Ramp type (two bits)
Time constant (four bits)
0000 = fastest
…
1111 = slowest
Data (28 bits): 5.23 format
Ramp Type 4—Constant Time (34-Bit Write)
The target word for the constant time ramp type is written in
five parts, with the 34-bit command written with six leading 0s
to extend the data write to five bytes. The parts of the constant
time target RAM write are
Ramp type (two bits).
Update step (one bit). Set to 1 when a new target is loaded
to trigger a step value update. The value is automatically
reset after the step value is updated.
Number of steps (three bits). The number of steps needed
to slew to the target value is set by these three bits, with the
number of steps equal to 23-bit setting + 6.
000 = 64
001 = 128
010 = 256
011 = 512
100 = 1024
101 = 2048
110 = 4096
111 = 8196
Data (16 bits): 2.14 format.
Reserved (12 bits). When writing to the RAM, set all of
these bits to 0.
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