參數(shù)資料
型號: ADAV4601BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 51/60頁
文件大小: 0K
描述: IC AUDIO CODEC PROCESSOR 80-LQFP
標準包裝: 1
系列: SigmaDSP®
類型: 音頻處理器
應(yīng)用: TV
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
ADAV4601
Rev. B | Page 55 of 60
Bit No.
Bit Name
Description
Default
Bit[2]
Clear mute
Set to 1 to unmute the ADAV4601 when the external pin has been used to mute the
part and the mute clear select bit is set. Having performed the required action, this bit
automatically resets to 0.
0
0b = no change
1b = clear pin mute
Bit[1]
Mute status (read-only)
Displays the status of the ADAV4601 mute.
0
0b = currently unmuting or unmuted
1b = currently muting or muted
Bit[0]
Mute flag (read-only)
Set to 1 when the ADAV4601 is in mute.
0
0b = unmuted
1b = muted
Address 0x0019 PWM Status Register (Default: 0x0000)
Table 55.
Bit No.
Bit Name
Description
Default
Bits[15:4]
Reserved
Always write as 0 if writing to this register.
000000000000
Bit[3]
PWM4 status
Set when the PWM4 outputs have gone from zero to 50/50 duty cycle.
0
0b = PWM4 disabled
1b = PWM4 enabled
Bits[2]
PWM3 status
Set when the PWM3 outputs have gone from zero to 50/50 duty cycle.
0
0b = PWM3 disabled
1b = PWM3 enabled
Bits[1]
PWM2 status
Set when the PWM2 outputs have gone from zero to 50/50 duty cycle.
0
0b = PWM2 disabled
1b = PWM2 enabled
Bit[0]
PWM1 status
Set when the PWM1 outputs have gone from zero to 50/50 duty cycle.
0
0b = PWM1 disabled
1b = PWM1 enabled
Address 0x001F PWM Control Register (Default: 0x1070)
Table 56.
Bit No.
Bit Name
Description
Default
Bits[15:14]
PWM ready configure
00b = PWM ready forced low
00
01b = PWM ready forced high
10b = PWM ready late
11b = PWM ready early
Bit[13]
Reserved
Always write as 0 if writing to this register.
0
Bit[12]
Reserved
Always write a 1 if writing to this register
1
Bits[11:7]
Reserved
Always write as 0 if writing to this register.
00000
Bits[6:4]
Reserved
Always write a 1 if writing to this register.
111
Bits[3:0]
Reserved
Always write as 0 if writing to this register.
0000
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