參數(shù)資料
型號： ADAV801ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/60頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標準包裝： 1
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調變： 無
動態(tài)范圍，標準 ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
配用： EVAL-ADAV801EBZ-ND - BOARD EVALUATION FOR ADAV801
ADAV801
Rev. A | Page 26 of 60
The size of the user bit buffer can be set by programming the
RxBCONF0 bit in the receiver buffer configuration register, as
shown in Table 11.
Table 11. RxBCONF3 Functionality
RxBCONF0
Receiver User Bit Buffer Size
0
384 bits with Preamble Z as the start of the block.
1
768 bits with Preamble Z as the start of the block.
The updating of the user bit buffer is controlled by Bits
RxBCONF[2:1] and Bit 7 to Bit 4 of the channel status register,
as shown in Table 12 and Table 13.
Table 12. RxBCONF[2:1] Functionality
RxBCONF
Bit 2
Bit 1
Receiver User Bit Buffer Configuration
0
User bits are ignored.
0
1
Update second buffer when first buffer is full.
1
0
Format according to Byte 1, Bit 4 to Bit 7, if
PRO bit is set. Format according to IEC60958-3,
if PRO bit is clear.
Table 13. Automatic User Bit Configuration
Bits
7
6
5
4
Automatic Receiver User Bit Buffer
Configuration
0
User bits are ignored.
0
1
0
AES-18 format: the user bit buffer is treated in
the same way as when RxBCONF[2:1] = 0b01.
1
0
User bit buffer is updated in the same way as
when RxBCONF[2:1] = 0b01 and RxBCONF0 =
0b00.
1
0
User-defined format: the user bit buffer is
treated in the same way as when
RxBCONF[2:1] = 0b01.
When the user bit buffer has been filled, the RxUBINT
interrupt bit in the interrupt status register is set, provided that
the RxUBINT mask bit is set, to indicate that the buffer has new
information and can be read.
For the special case when the user data is formatted according
to the IEC 60958-3 standard into messages made of information
units, called IUs, the zeros stuffed between each IU and each
message are removed and only the IUs are stored. Once the end
of the message is sensed by more that eight zeros between IUs,
the user bit buffer is updated with the complete message and
the first buffer begins looking for the start of the next message.
Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and
W bits (see the IEC 60958-3 specification for more information).
When 96 IUs are received, the Q subcode of the IUs is stored in
the Q subcode buffer, consisting of 10 bytes. The Q subcode is
the Q bits taken from each of the 96 IUs. The first 10 bytes
(80 bits) of the Q subcode contain information sent by CD, MD,
and DAT systems. The last 16 bits of the Q subcode are used to
perform a CRC check of the Q subcode. If an error occurs in
the CRC check of the Q subcode, the QCRCERROR bit is set.
This is a sticky bit that remains high until the register is read.
Transmitter Operation
The S/PDIF transmitter has a similar buffer structure to the
receive section. The transmitter channel status buffer occupies
24 bytes of the register map. This buffer is long enough to store
the 192 bits required for one channel of channel status informa-
tion. Setting the TxCSSWITCH bit determines if the data
loaded to the transmitter channel status buffer is intended for
Channel A or Channel B. In most cases, the channel status bits
for Channel A and Channel B are the same, in which case
setting the Tx_A/B_Same bit reads the data from the trans-
mitter channel status buffer and transmits it on both channels.
Because the channel status information is rarely changed during
transmission, the information contained in the buffer is trans-
mitted repeatedly. The Disable_Tx_Copy bit can be used to
prevent the channel status bits from being copied from the
transmitter CS buffer into the S/PDIF transmitter buffer until
the user has finished loading the buffers. This feature is
typically used, if the Channel A data and Channel B data are
different. Setting the bit prevents the data from being copied.
Clearing the bit allows the data to be copied and then
transmitted. Figure 48 shows how the buffers are organized.
04
57
7-
0
2
8
TxCSSWITCH
TRANSMIT
CS BUFFER
(0x38 TO 0x4F)
CHANNEL
STATUS A
(24 × 8 BITS)
CHANNEL
STATUS B
(24 × 8 BITS)
DITOUT
S/PDIF
TRANSMIT
BUFFER
Figure 48. Transmitter Channel Status Buffer
As with the receiver section, the transmitted user bits are also
double-buffered. This is required because, unlike the channel
status bits, the user bits do not necessarily repeat themselves.
The user bits can be buffered in various configurations, as listed
in Table 14. Transmission of the user bits is determined by the
state of the BCONF3 bit. If the bit is 0, the user bits begin
transmitting right away without alignment to the Z preamble. If
this bit is 1, the user bits do not start transmitting until a
Z preamble occurs when the TxBCONF[2:1] bits are 01.
Table 14. Transmitter User Bit Buffer Configurations
TxBCONF[2:1]
Bit 2
Bit 1
Transmitter User Bit Buffer Configuration
0
Zeros are transmitted for the user bits.
0
1
Host writes user bits to the buffer until it is full.
1
0
Writes the user bits to the buffer in IUs
specified by IEC60958-3 and transmits them
according to the standard.
1
First 10 bytes of the user-bit buffer are
configured to store a Q subcode.
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ADAV801ASTZ-REEL 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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