參數(shù)資料
型號： ADC1112D125HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 11-bit ADC; CMOS or LVDS DDR digital outputs
封裝： ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù)： 11/41頁
文件大?。?/td> 565K
代理商： ADC1112D125HN
ADC1112D125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 March 2011
11 of 41
NXP Semiconductors
ADC1112D125
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
[1]
Typical values measured at V
DDA
= 3 V, V
DDO
= 1.8 V, T
amb
= 25
°
C; minimum and maximum values are across the full temperature
range T
amb
=
40
°
C to +85
°
C at V
DDA
= 3 V, V
DDO
= 1.8 V; V
INAP
V
INAM
=
1 dBFS; V
INBP
V
INBM
=
1 dBFS; unless otherwise
specified.
[2]
Measured between 20 % to 80 % of V
DDO
.
Rise time measured from
50 mV to +50 mV; fall time measured from +50 mV to
50 mV.
[3]
Table 8.
Symbol
Clock timing input: pins CLKP and CLKM
f
clk
clock frequency
t
lat(data)
data latency time
Clock and digital output timing characteristics
[1]
Parameter
Conditions
Min
Typ
Max
Unit
100
-
-
14
125
-
MHz
clock
cycles
%
%
ns
μ
s
δ
clk
clock duty cycle
DCS_EN = 1
DCS_EN = 0
30
45
-
-
50
50
0.8
76
70
55
-
-
t
d(s)
t
wake
CMOS mode timing: pins DA10 to DA0, DB10 to DB0 and DAV
t
PD
propagation delay
sampling delay time
wake-up time
DATA
DAV
-
-
-
-
3.9
4.2
5.7
1.4
-
-
-
-
-
-
-
2.4
2.4
2.4
ns
ns
ns
ns
ns
ns
ns
t
su
t
h
t
r
set-up time
hold time
rise time
DATA
DAV
DATA
[2]
0.5
0.5
t
f
LVDS DDR mode timing: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10 M to LOW_DA0_M,
DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM
t
PD
propagation delay
fall time
[2]
0.5
DATA
DAV
-
-
-
-
3.9
4.2
1.4
2.0
100
100
100
100
-
-
-
-
200
200
200
200
ns
ns
ns
ns
ps
ps
ps
ps
t
su
t
h
t
r
set-up time
hold time
rise time
DATA
DAV
DATA
DAV
[3]
50
50
t
f
fall time
[3]
50
50
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ADC1112D125HN/C1+551 制造商:NXP Semiconductors 功能描述:Bulk 制造商:NXP Semiconductors 功能描述:0
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