參數(shù)資料
型號: ADC12281
廠商: National Semiconductor Corporation
英文描述: 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線式A/D轉(zhuǎn)換器)
中文描述: 12位,20 MSPS的單端輸入,流水線A / D轉(zhuǎn)換器(12位20 MSPS的單端輸入管線式的A / D轉(zhuǎn)換器)
文件頁數(shù): 12/16頁
文件大?。?/td> 322K
代理商: ADC12281
Functional Description
The ADC12881 is a monolithic CMOS analog-to-analog con-
verter capable of converting single-ended analog input sig-
nals into 12-bit digital words at 20 megasamples per second
(MSPS). This device utilizes a proprietary pipeline architec-
ture and algorithm to minimize die size and power dissipa-
tion. The ADC12281 uses self-calibration and digital error
correction to maintain accuracy and performance over tem-
perature and a single-ended to differential conversion circuit
to ease input interfacing while achieving differential input
performance.
The ADC12281 has an input signal sample-and-hold ampli-
fier and internal reference buffer. The analog input and the
reference voltage are converted to differential signals for in-
ternal use. Using differential signals in the analog conversion
core reduces crosstalk and noise pickup from the digital sec-
tion and power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue”) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally-generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent er-
rors in the analog conversion blocks such as op amp offsets,
comparator offsets, capacitor mismatches, etc. The calibra-
tion procedure determines coefficients for each digital output
bit from the conversion core and stores these coefficients in
on-chip RAM. The digital correction module uses the coeffi-
cients in RAM to convert the raw data bits from the conver-
sion core into the 12-bit digital output code.
Applications Information
1.0 ANALOG INPUTS.
The analog inputs of the ADC12881
are the reference input (V
REF
) and the signal input (V
IN
).
1.1 Reference Input.
The V
REF
input must be driven from an
accurate, stable reference voltage source between 1.8V and
2.2V and bypassed to a clean, low-noise ground with a
monolithic ceramic capacitor (nominally 0.01 μF).
1.2 Analog Signal Input.
This analog input is a switch fol-
lowed by an integrator. The input capacitance changes with
the clock level, appearing as 10 pF when the clock is low,
and 15 pF when the clock is high. Since a dynamic capaci-
tance is more difficult to drive than is a fixed capacitance,
choose an amplifier that can drive this type of load. The
CLC409 has been found to be a good device to drive the
ADC12281. Do not drive the input beyond the supply rails.
The V
input must be driven with a low impedance signal
source that does not add any distortion to the input signal.
The ground reference for the V
input is the V
pin.
The V
pin should be connected to a clean point in the
analog ground plane. The ground return for the reference
voltage should enter the ground plane at the same point as
does the V
IN COM
pin.
To simplify the interface, the ADC12281 has an internal
single-ended to differential buffer. This permits performance
you would expect to see with a differential input while driving
the input with a single-ended signal.
To achieve maximum performance, you should be careful to
maintain short input and ground runs in lines carrying signal
current. The signal ground line, V
IN COM
and the reference
ground should all enter the analog ground plane at the same
point, as indicated in Figure 5
A
www.national.com
12
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