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參數(shù)資料
| 型號(hào)： | ADC12281 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線(xiàn)式A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，20 MSPS的單端輸入，流水線(xiàn)A / D轉(zhuǎn)換器（12位20 MSPS的單端輸入管線(xiàn)式的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12281 |
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Applications Information
(Continued)
Powering the V
I/O from 3V will also reduce power con-
sumption and noise generation due to output switching.
DO
NOT operate the V
D
I/O at a voltage higher than V
D
or V
A
!
Also helpful in minimizing noise due to output switching is to
minimize the currents at the digital outputs. This can be done
by connecting buffers between the ADC outputs and any
other circuitry. Only one buffer should be connected to each
output. Additionally, inserting series resistors of 47
to 56
right at the digital outputs, close to the ADC pins, will isolate
the outputs from other circuitry and limit output currents.
4.0 POWER SUPPLY CONSIDERATIONS
Each power pin should be bypassed with a parallel combina-
tion of a 10 μF capacitor and a 0.1 μF ceramic chip capacitor.
The chip capacitors should be within 1/2 centimeter of the
power pins. Leadless chip capacitors are preferred because
they provide low lead inductance.
The converter’s digital logic supply (V
) should be well iso-
lated from the supply that is used for other digital circuitry on
the board. A common power supply should be used for both
V
A
(analog supply) and V
D
(digital supply), and each of these
supply pins should be separately bypassed with a 0.1 μF ce-
ramic capacitor and a low ESR 10 μF electrolytic capacitor.A
ferrite bead or inductor should be used between V
A
and V
D
to prevent noise coupling from the digital supply into the ana-
log circuit.
V
I/O is the power pin for the output buffers. This pin may
be supplied with a potential between 3.0V and 5V. This
makes it easy to interface the ADC12281 with 3V or 5V logic
families.
The voltage at V
I/O should never exceed the voltage at ei-
ther V
or V
. All power supplies connected to the device
should be applied simultaneously.
As is the case with all high speed converters, the ADC12281
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC12281 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never over-
lap each other. Separation between the analog and digital
ground planes should be at least 1/8 inch, were possible.
The ground return for the digital supply (DGND I/O) carries
the ground current for the output drivers. The output current
can exhibit high transients that could add noise to the con-
version process. To prevent this from happening, the DGND
I/O pin should NOT be connected to system ground in close
proximity to any of the ADC12281’s ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry sepa-
rated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signifi-
cant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or sig-
nal edges, like the 74F and the 74AC(T) families.
DS101027-29
FIGURE 6. Example of a Suitable Layout
A
www.national.com
14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADC12281CIVT | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
| ADC12281EVAL | 功能描述:BOARD EVALUATION FOR ADC12281 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類(lèi)型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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| ADC122S021CIMM | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC122S021CIMM/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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