參數(shù)資料
型號: ADC12281
廠商: National Semiconductor Corporation
英文描述: 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線式A/D轉(zhuǎn)換器)
中文描述: 12位,20 MSPS的單端輸入,流水線A / D轉(zhuǎn)換器(12位20 MSPS的單端輸入管線式的A / D轉(zhuǎn)換器)
文件頁數(shù): 13/16頁
文件大?。?/td> 322K
代理商: ADC12281
Applications Information
(Continued)
2.0 DIGITAL INPUTS.
TheADC12281 has four digital inputs.
They are CLOCK, CAL, OE and PD.
2.1
The
CLOCK
input should be driven with a stable, low
phase jitter TTL level clock signal in the range of 0.5 MHz to
20 MHz. The clock high level should be limited to 3 V
for
maximum SNR performance and to meet data sheet perfor-
mance specifications. The trace carrying the clock signal
should be as short as possible. This trace should not cross
any other signal line, analog or digital, not even at 90.
2.2
The level sensitive
CAL
input must be pulsed high for at
least three clock cycles to begin ADC calibration. For best
performance, calibration should be performed about ten sec-
onds after power up, after resetting the ADC and whenever
the temperature has changed by more than 25C since the
last calibration cycle. Calibration should be performed at the
same clock frequency that will be used for conversions.
Calibration takes 4000 clock cycles to be performed.
Irrel-
evant data may appear at the data outputs during CAL.
2.3 The OE pin
is used to READ the conversion. When the
OE pin is low, the output buffers return to the active state.
When the OE input is high, the output buffers are in the high
impedance state.
2.4 The PD pin
, when high, holds the ADC12281 in a
power-down mode where power consumption is typically
less than 15 mW to conserve power when the converter is
not being used. The ADC12281 will begin normal operation
with t
PD
after this pin is brought low, provided a valid CLOCK
input is present. The data in the pipeline is corrupted while in
the power-down mode. The ADC12281 does not have to be
re-calibrated after a power-down cycle unless the power
supply voltage or ambient temperature has changed.
3.0 OUTPUTS
The ADC12281 has three analog outputs: reference output
voltages V
, V
, and V
. There are 14 digital outputs: 12
Data Output pins, OR (Over-range) and Ready.
3.1 The reference output voltages
are made available only
for the purpose of bypassing with capacitors to a clean ana-
log ground. The recommended bypass capacitors are 0.1 μF
ceramic chip capacitors.
DO NOT LOAD
reference bypass pins 30, 31 or 32.
3.2 The OR output
goes low to indicate the presence of
valid data at the output data lines. The signal will go high
when the analog input is above the V
REF
input or below
GND.
3.3 The READY output
, when at a logic high, indicates that
the ADC12281 is ready to convert. This output is at a logic
low during a calibration cycle and when the ADC12281 is in
the power down mode.
3.4 The Data Outputs
are TTL/CMOS compatible. The out-
put data format is 12 bits straight binary. The V
I/O provides
power for the output driver and may be operated from a sup-
ply in the range of 3.0V to the V
D
supply (nominal 5V). This
can simplify interfacing to 3.0V devices and systems.
DS101027-28
FIGURE 5. Suggested Application Circuit
A
www.national.com
13
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