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參數(shù)資料
| 型號： | ADC12281CIVT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 368K |
| 代理商： | ADC12281CIVT |
Specification Definitions
APERTURE JITTER
is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY
See Sampling Delay.
CLOCK DUTY CYCLE
is the ratio of the time that the clock
waveform is high to the total time for one clock cycle.
CONVERSION LATENCY:
See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL)
is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS)
is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD -
1.76)/6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL SCALE ERROR
is the difference between the input
voltage (V
–V
IN
) just causing a transition to positive full
scale and V
REF
1.5 LSB, where V
REF
is (V
REF+ IN
) –
(V
REF IN
).
FULL POWER BANDWIDTH
is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
INTEGRAL NON-LINEARITY (INL)
is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
2
LSB below the first code transition)
through positive full scale (the last code transition). The
deviation of any given code from this straight line is mea-
sured from the center of that code value. The end point test
method is used. INL is commonly measured at rated clock
frequency with a ramp input.
OFFSET ERROR
is the difference between the ideal LSB
transition to the actual transition point. The LSB transition
should occur when V
IN+
= V
IN
.
PIPELINE DELAY (LATENCY)
is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay plus the Output Delay.
SAMPLING (APERTURE) DELAY
is the time after the edge
of the clock to when the input signal is acquired or held for
conversion.
SIGNAL TO NOISE RATIO (SNR)
is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD)
is the ratio, ex-
pressed in dB or dBc, of the rms total of the first six harmonic
components to the rms value of the input signal.
ZERO SCALE OFFSET ERROR
is the difference between
the ideal input voltage (
1
2
LSB) and the actual input voltage
that just causes a transition from an output code of zero to
an output code of one.
ZERO ERROR
See Zero Scale Offset Error.
Functional Description
The ADC12881 is a monolithic CMOS analog-to-analog con-
verter capable of converting single-ended analog input sig-
nals into 12-bit digital words at 20 megasamples per second
(MSPS). This device utilizes a proprietary pipeline architec-
ture and algorithm to minimize die size and power dissipa-
tion. The ADC12281 uses self-calibration and digital error
correction to maintain accuracy and performance over tem-
perature and a single-ended to differential conversion circuit
to ease input interfacing while achieving differential input
performance.
The ADC12281 has an input signal sample-and-hold ampli-
fier and internal reference buffer. The analog input and the
reference voltage are converted to differential signals for
internal use. Using differential signals in the analog conver-
sion core reduces crosstalk and noise pickup from the digital
section and power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue”) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally-generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent
errors in the analog conversion blocks such as op amp
offsets, comparator offsets, capacitor mismatches, etc. The
calibration procedure determines coefficients for each digital
output bit from the conversion core and stores these coeffi-
cients in on-chip RAM. The digital correction module uses
the coefficients in RAM to convert the raw data bits from the
conversion core into the 12-bit digital output code.
Applications Information
1.0 ANALOG INPUTS
The analog inputs of the ADC12881 are the reference input
(V
REF
) and the signal input (V
IN
).
Reference Input
The V
input must be driven from an accurate, stable
reference voltage source between 1.8V and 2.2V and by-
passed to a clean, low-noise ground with a monolithic ce-
ramic capacitor (nominally 0.01 μF).
Analog Signal Input
This analog input is a switch followed by an integrator. The
input capacitance changes with the clock level, appearing as
10 pF when the clock is low, and 15 pF when the clock is
high. Since a dynamic capacitance is more difficult to drive
than is a fixed capacitance, choose an amplifier that can
drive this type of load. The CLC409 has been found to be a
good device to drive the ADC12281. Do not drive the input
beyond the supply rails.
The V
IN
input must be driven with a low impedance signal
source that does not add any distortion to the input signal.
The ground reference for the V
IN
input is the V
IN COM
pin.
The V
IN COM
pin should be connected to a clean point in the
A
www.national.com
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