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參數資料
| 型號： | ADC12281CIVT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數： | 14/16頁 |
| 文件大?。?/td> | 368K |
| 代理商： | ADC12281CIVT |
Applications Information
(Continued)
3.0 OUTPUTS
The ADC12281 has three analog outputs: reference output
voltages V
RN
, V
RM
, and V
RP
. There are 14 digital outputs: 12
Data Output pins, OR (Over-range) and Ready.
The reference output voltages
are made available only for
the purpose of bypassing with capacitors to a clean analog
ground. The recommended bypass capacitors are 0.1 μF
ceramic chip capacitors.
DO NOT LOAD
reference bypass pins 30, 31 or 32.
The OR output
goes low to indicate the presence of valid
data at the output data lines. The signal will go high when the
analog input is above the V
REF
input or below GND.
The READY output
, when at a logic high, indicates that the
ADC12281 is ready to convert. This output is at a logic low
during a calibration cycle and when the ADC12281 is in the
power down mode.
The Data Outputs
are TTL/CMOS compatible. The output
data format is 12 bits straight binary. The V
I/O provides
power for the output driver and may be operated from a
supply in the range of 3.0V to the V
supply (nominal 5V).
This can simplify interfacing to 3.0V devices and systems.
Powering the V
I/O from 3V will also reduce power con-
sumption and noise generation due to output switching.
DO
NOT operate the V
D
I/O at a voltage higher than V
D
or V
A
!
Also helpful in minimizing noise due to output switching is to
minimize the currents at the digital outputs. This can be done
by connecting buffers between the ADC outputs and any
other circuitry. Only one buffer should be connected to each
output. Additionally, inserting series resistors of 47
to 56
right at the digital outputs, close to the ADC pins, will isolate
the outputs from other circuitry and limit output currents.
4.0 POWER SUPPLY CONSIDERATIONS
Each power pin should be bypassed with a parallel combi-
nation of a 10 μF capacitor and a 0.1 μF ceramic chip
capacitor. The chip capacitors should be within 1/2 centime-
ter of the power pins. Leadless chip capacitors are preferred
because they provide low lead inductance.
The converter’s digital logic supply (V
) should be well iso-
lated from the supply that is used for other digital circuitry on
the board. A common power supply should be used for both
V
(analog supply) and V
(digital supply), and each of these
supply pins should be separately bypassed with a 0.1 μF
ceramic capacitor and a low ESR 10 μF electrolytic capaci-
tor. A ferrite bead or inductor should be used between V
A
and V
to prevent noise coupling from the digital supply into
the analog circuit.
V
I/O is the power pin for the output buffers. This pin may
be supplied with a potential between 2.7V and V
. This
makes it easy to interface the ADC12281 with 3V or 5V logic
families.
The voltage at V
D
I/O should never exceed the voltage at
either V
A
or V
D
. All power supplies connected to the device
should be applied simultaneously.
As is the case with all high speed converters, the ADC12281
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC12281 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never
overlap each other. Separation between the analog and
digital ground planes should be at least 1/8 inch, were pos-
sible.
The ground return for the digital supply (DGND I/O) carries
the ground current for the output drivers. The output current
can exhibit high transients that could add noise to the con-
version process. To prevent this from happening, the DGND
I/O pin should NOT be connected to system ground in close
proximity to any of the ADC12281’s ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry sepa-
rated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients dur-
ing clock or signal edges, like the 74F and the 74AC(T)
families.
A
www.national.com
14
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