參數(shù)資料
型號: ADC12281CIVT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: TQFP-32
文件頁數(shù): 3/16頁
文件大?。?/td> 368K
代理商: ADC12281CIVT
Pin Descriptions and Equivalent Circuits
(Continued)
Pin
Symbol
Equivalent Circuit
Description
32
V
RP
Positive reference bypass pin. Bypass with a 0.1 μF
capacitor. Do not connect anything else to this pin.
See Section 3.1.
31
V
RM
Reference midpoint bypass pin. Bypass with a
0.1 μF capacitor. Do not connect anything else to
this pin. See Section 3.1.
30
V
RN
Negative reference bypass pin. Bypass with a
0.1 μF capacitor. Do not connect anything else to
this pin. See Section 3.1.
10
CLOCK
Sample clock input, TTL compatible. Amplitude
should not exceed 3 V
P-P
.
Calibration request, active High. Calibration cycle
starts when CAL returns to logic low. CAL is
ignored during power-down mode. See Section 2.2.
Power-down, active High, ignored during calibration
cycle. See paragraph 2.4.
Output enable control, active low. When this pin is
high the data outputs are in TRI-STATE
(high-impedance) mode.
8
CAL
7
PD
11
OE
28
OR
Over-range indicator. This pin is at a logic High, for
V
IN
<
0 or for V
IN
>
V
REF
.
29
READY
Device ready indicator, active High. This pin will be
at a logic Low during a calibration cycle and while
the device is in the power down mode.
14–19,
22–27
D0–D11
Digital output word, CMOS compatible. D0 (pin 19)
is LSB, D11 (pin 36) is MSB. Load with no more
than 25 pF.
A
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