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參數(shù)資料
| 型號(hào)： | ADC12281CIVT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 368K |
| 代理商： | ADC12281CIVT |
Applications Information
(Continued)
analog ground plane. The ground return for the reference
voltage should enter the ground plane at the same point as
does the V
IN COM
pin.
To simplify the interface, the ADC12281 has an internal
single-ended to differential buffer. This permits performance
you would expect to see with a differential input while driving
the input with a single-ended signal.
To achieve maximum performance, you should be careful to
maintain short input and ground runs in lines carrying signal
current. The signal ground line, V
and the reference
ground should all enter the analog ground plane at the same
point, as indicated in
Figure 5
.
2.0 DIGITAL INPUTS
The ADC12281 has four digital inputs. They are CLOCK,
CAL, OE and PD.
The
CLOCK
input should be driven with a stable, low phase
jitter TTL level clock signal in the range of 0.5 MHz to 20
MHz. The clock high level should be limited to 3 V
for
maximum SNR performance and to meet data sheet perfor-
mance specifications. The trace carrying the clock signal
should be as short as possible. This trace should not cross
any other signal line, analog or digital, not even at 90.
The level sensitive
CAL
input must be pulsed high for at
least three clock cycles to begin ADC calibration. For best
performance, calibration should be performed about ten sec-
onds after power up, after resetting the ADC and whenever
the temperature has changed by more than 25C since the
last calibration cycle. Calibration should be performed at the
same clock frequency that will be used for conversions.
Calibration takes 4000 clock cycles to be performed.
Irrel-
evant data may appear at the data outputs during CAL.
The OE pin
is used to READ the conversion. When the OE
pin is low, the output buffers return to the active state. When
the OE input is high, the output buffers are in the high
impedance state.
The PD pin
, when high, holds the ADC12281 in a
power-down mode where power consumption is typically
less than 15 mW to conserve power when the converter is
not being used. The ADC12281 will begin normal operation
with t
PD
after this pin is brought low, provided a valid CLOCK
input is present. The data in the pipeline is corrupted while in
the power-down mode. The ADC12281 does not have to be
re-calibrated after a power-down cycle unless the power
supply voltage or ambient temperature has changed.
10102728
FIGURE 5. Suggested Application Circuit
A
www.national.com
13
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| ADC122S021CIMMX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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