- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9101 > ADF4156BCPZ-RL7 (Analog Devices Inc)IC PLL FRAC-N FREQ SYNTH 20LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADF4156BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FRAC-N FREQ SYNTH 20LFCSP |
| 產(chǎn)品變化通告： | Improve Phase Noise Performance |
| 設(shè)計(jì)資源： | Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6.2GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4156
Rev. E | Page 19 of 24
ADF4156
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
058
63-
0
23
Figure 22. Topology 1—Fast-Lock Loop Filter Topology
ADF4156
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
058
63-
0
24
Figure 23. Topology 2—Fast-Lock Loop Filter Topology
SPUR MECHANISMS
This section describes the three spur mechanisms that arise
with a fractional-N synthesizer and how to minimize these
spurs in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third-order Σ-Δ
modulator with a modulus (MOD) that is programmable to any
integer value from 2 to 4095. In low spur mode (dither enabled),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (fPFD) that allows PLL output
frequencies to be synthesized at a channel step resolution of
fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4156, the repeat length depends on the value of MOD,
as listed in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition
Repeat
Length
Spur Interval
If MOD is divisible by 2, but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3, but not 2
3 × MOD
Channel step/3
If MOD is divisible by 6
6 × MOD
Channel step/6
Otherwise
MOD
Channel step
In low spur mode (dither enabled), the repeat length is extended
to 221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum look like broadband noise. As a
result, the in-band phase noise at the PLL output can be degraded
by as much as 10 dB. Therefore, for lowest noise, keeping dither
off is a better choice, particularly when the final loop bandwidth is
low enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (as is the case
with fractional-N synthesizers), spur sidebands appear on the
VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an
integer multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth, hence the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop can cause a problem. One such mechanism is
feedthrough of low levels of switching noise from the on-chip
reference through the RFIN pin and back to the VCO, resulting
in reference spur levels as high as 90 dBc. Care should be taken in
the PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization
noise of the Σ-Δ modulator also depends on the phase word set
as the starting point of the modulator. Setting the Σ-Δ reset bit
(DB14 in Register R3) to 0 ensures that this starting point is used
for the Σ-Δ modulator on every write to Register R0.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Therefore,
a look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4156.
The evaluation software has a sweep function to sweep the
phase word so that the user can observe the spur levels on a
spectrum analyzer.
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on a particular frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-2TW-IV | CONVERTER MOD DC/DC 5.5V 150W |
| ADF4360-9BCPZRL | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| VI-2T0-IV | CONVERTER MOD DC/DC 5V 150W |
| ISPPAC-CLK5308S-01T48C | IC BUFFER FANOUT ISP UNIV 48TQFP |
| VE-274-MW-S | CONVERTER MOD DC/DC 48V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4156BCPZ-U1 | 制造商:Analog Devices 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Trays |
| ADF4156BRUZ | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4156BRUZ-RL | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156BRUZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。