參數(shù)資料
型號(hào): ISPPAC-CLK5308S-01T48C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 1/56頁
文件大?。?/td> 0K
描述: IC BUFFER FANOUT ISP UNIV 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
www.latticesemi.com
1
DS1010_01.4
October 2007
Preliminary Data Sheet DS1010
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
ispClock 5300S Family
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
Features
■ Four Operating Congurations
Zero delay buffer
Zero delay and non-zero delay buffer
Dual non-zero delay buffer
Non-zero delay buffer with output divider
■ 8MHz to 267MHz Input/Output Operation
■ Low Output to Output Skew (<100ps)
■ Low Jitter Peak-to-Peak (< 70 ps)
■ Up to 20 Programmable Fan-out Buffers
Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Programmable output impedance
- 40 to 70Ω in 5Ω increments
Programmable slew rate
Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
Programmable lock detect
Three “Power of 2” output dividers (5-bit)
Programmable on-chip loop lter
Compatible with spread spectrum clocks
Internal/external feedback
■ Precision Programmable Phase Adjustment
(Skew) Per Output
8 settings; minimum step size 156ps
- Locked to VCO frequency
Up to +/- 5ns skew range
Coarse and ne adjustment modes
■ Up to Three Clock Frequency Domains
■ Flexible Clock Reference and External
Feedback Inputs
Programmable single-ended or differential input
reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
Clock A/B selection multiplexer
Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
Programmable termination
■ All Inputs and Outputs are Hot Socket
Compliant
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 48-pin and 64-pin TQFP Packages
■ Applications
Circuit board common clock distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer
ispClock5300S Family Functional Diagram
VCO
LOOP
FILTER
PHASE
FREQ.
DETECT
REFA /
+
REFP
REFSEL
1
0
S
A
P
Y
B
_
L
P
K
C
O
L
SKEW
CONTROL
OUTPUT 1
OUTPUT N
OUTPUT
DRIVERS
OUTPUT
DIVIDERS
V1
V2
V0
5-bit
5-Bit
5-bit
0
1
FBK
REFB /
REFN
OUTPUT
ROUTING
MATRIX
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參數(shù)描述
ISPPACCLK5308S-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5308S-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5308S-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5308S-01T64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5308S-01T64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended