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參數(shù)資料
| 型號： | ADF4156BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FRAC-N FREQ SYNTH 20LFCSP |
| 產(chǎn)品變化通告： | Improve Phase Noise Performance |
| 設(shè)計資源： | Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6.2GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
ADF4156
Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AVDD
RFINA
RFINB
RSET
DVDD
MUXOUT
LE
CE
REFIN
DGND
CLOCK
DATA
VP
ADF4156
TOP VIEW
(Not to Scale)
05863-
003
Figure 3. TSSOP Pin Configuration
PIN 1
INDICATOR
1
CPGND
2
AGND
3
AGND
4
RFINB
5
RFINA
13 DATA
14 LE
15 MUXOUT
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
12 CLOCK
11 CE
6
A
V
DD
7
A
V
DD
8
RE
F
IN
10
DG
ND
9
DG
ND
18
V
P
19
R
SET
20
C
P
17
DV
DD
16
DV
DD
TOP VIEW
(Not to Scale)
ADF4156
05863-
004
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
RSET
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The
relationship between ICP and RSET is
SET
CPmax
R
I
5
.
25
=
where RSET = 5.1 kΩ and ICPmax = 5 mA.
2
20
CP
Charge-Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives
the external VCO.
3
1
CPGND
Charge-Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF.
6
5
RFINA
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode.
11
12
CLOCK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch.
14
15
MUXOUT
Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally.
15
16, 17
DVDD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD.
16
18
VP
Charge-Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
EPAD
The exposed pad must be connected to ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4156BCPZ-U1 | 制造商:Analog Devices 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Trays |
| ADF4156BRUZ | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4156BRUZ-RL | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156BRUZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
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