- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9159 > ADF4158CCPZ (Analog Devices Inc)IC FRACTION N FREQ SYNT 24LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADF4158CCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACTION N FREQ SYNT 24LFCSP |
| 標準包裝： | 1 |
| 類型： | 分數(shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6.1GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | * |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Data Sheet
ADF4158
Rev. G | Page 29 of 36
An example of ramp with FSK on the top of it is shown in
Figure 37. Eventually, the ramp must be activated as described
in Activating the Ramp section.
08728-
025
FR
E
Q
U
E
N
C
Y
0RAMP END
F
R
EQ
U
EN
C
Y
SW
EEP
FSK SHIFT
TIME
LFM STEP =
FREQUENCY
SWEEP/NUMBER
OF STEPS
Figure 37. Combined FSK and LFM Waveform (N Corresponds to the
Number of LFM Steps)
Delayed Start
A delayed start can be used with two different parts to control
the start time. The idea of delayed start is shown in Figure 38.
FR
E
Q
U
E
N
C
Y
TIME
RAMP WITH
DELAYED START
RAMP WITHOUT
DELAYED START
08
728
-12
6
Figure 38. Delayed Start of Sawtooth Ramp
Example
For example, to program a delayed start with two different parts
to control the start time,
1.
Set DB15 in Register R7 to 1 to enable the delayed start of
ramp option.
2.
Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp on
the first part is delayed by 5 μs, fPFD = 25 MHz. The delay is
calculated as follows:
Delay = tPFD × Delay Start Word
= 40 ns × 125 = 5 μs
3.
Set Bit DB16 in Register R7 to 1 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp
on the second part is delayed by 125 μs. Use the following
formula for calculating the delay:
Delay = tPFD × CLK1 × Delay Start Word
= 40 ns × 25 × 125 = 125 μs
Eventually, the ramp must be activated as described in
Delay Between Ramps
This feature adds a delay between bursts in ramp. Figure 39
shows a delay between ramps in sawtooth mode.
FR
E
Q
U
E
N
C
Y
TIME
DELAY
08
72
8-
02
8
Figure 39. Delay Between Ramps for Sawtooth Mode
Example
For example, to add a delay between bursts in a ramp,
1.
Set DB17 in Register R7 to 1 to enable delay between
ramps option.
2.
Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp
by 5 μs, fPFD = 25 MHz. The delay is calculated as follows:
Delay = tPFD × Delay Start Word
= 40 ns × 125 = 5 μs
If a longer delay is needed, for example, 125 μs, Bit DB16
in Register R7 should be set to 1 and the 12-bit delay start
word (DB[14:3] in Register R7) should be set to 125. The
delay is calculated as follows
Delay = tPFD × CLK1 × Delay Start Word
= 40 ns × 25 × 125 = 125 μs
There is also a possibility to activate fast-lock operation for the
first period of delay. This is done by setting Bit DB18 in Register R7
to 1. This feature is useful for sawtooth ramps to mitigate the
frequency overshoot on the transition from one sawtooth to the
next. Eventually, the ramp must be activated as described in
Nonlinear Ramp Mode
The ADF4158 is capable of generating a parabolic ramp. The
output frequency is generated according to the following
equation:
fOUT(n + 1) = fOUT(n) + n × fDEV
(16)
where:
fOUT is output frequency.
n is step number.
fDEV is frequency deviation.
FR
E
Q
U
E
N
C
Y
TIME
087
28-
029
Figure 40. Parabolic Ramp
相關PDF資料 |
PDF描述 |
|---|---|
| 74VHC153MTC | MULTIPLEXER DUAL 4IN 16TSSOP |
| PI5C3257WE | IC QUAD 2:1 MUX/DEMUX 16-SOIC |
| SY100E222LTY | IC CLOCK GEN/BUFF LVPECL 52LQFP |
| FST16861MTDX | IC SWITCH BUS 20BIT TTL 48TSSOP |
| VE-B20-MY-F4 | CONVERTER MOD DC/DC 5V 50W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4158CCPZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 6.1GHZ, LFCS |
| ADF4158CCPZ-RL7 | 功能描述:IC FRACTION N FREQ SYNT 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4158WCCPZ | 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:分數(shù) N 合成器（RF） PLL:是 輸入:CMOS，TTL 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/無 頻率 - 最大值:6.1GHz 分頻器/倍頻器:是/是 電壓 - 電源:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-WFQFN 裸露焊盤 供應商器件封裝:24-LFCSP-WQ（4x4） 標準包裝:1 |
| ADF4158WCCPZ-RL7 | 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4159 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復。