- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373982 > ADF4193BCPZ (ANALOG DEVICES INC) Low Phase Noise, Fast Settling PLL Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | ADF4193BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 437K |
| 代理商： | ADF4193BCPZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
ADF4193
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Thereafter, program the
INT and FRAC words for the desired RF output frequency. See
the Worked Example section for more information.
Rev. B | Page 12 of 28
PFD and Charge Pump
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
proportional to the phase difference between the inputs. The
charge pump outputs a net up or down current pulse of a width
equal to this difference, to pump up or pump down the voltage
that is integrated onto the loop filter, which in turn increases or
decreases the VCO output frequency. If the N divider phase lags
the R divider phase, a net up current pulse is produced that
increases the VCO frequency (and thus the phase). If the
N divider phase leads the R divider edge, then a net down pulse
is produced to reduce the VCO frequency and phase. Figure 23
is a simplified schematic of the PFD and charge pump. The
charge pump is made up of an array of 64 identical cells, each of
which is fully differential. All 64 cells are active during fast lock,
but only one is active during normal operation. Because a
single-ended control voltage is required to tune the VCO, an
on-chip, differential-to-single-ended amplifier is provided for
this purpose. In addition, because the phase-lock loop only
controls the differential voltage generated across the charge
pump outputs, an internal common-mode feedback (CMFB)
loop biases the charge pump outputs at a common-mode
voltage of approximately 2 V.
0
CLR
Q
D
R DIVIDER
N DIVIDER
CHARGE
PUMP
ARRAY
[64:1]
CMFB
EN[64:1]
CLR
Q
D
CP
OUT+
CP
OUT–
Figure 23. PFD and Differential Charge Pump Simplified Schematic
Differential Charge Pump
The charge pump cell (see Figure 24) has a fully differential
design for best up-to-down current matching. Good matching
is essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
To pump up, the up switches are on and PMOS current is
sourced out through CP
OUT+
; this increases the voltage on the
external loop filter capacitors connected to CP
OUT+
. Similarly,
the NMOS current sink on CP
OUT
decreases the voltage on the
external loop filter capacitors connected to CP
OUT
. Therefore,
the differential voltage between CP
OUT+
and CP
OUT
increases.
To pump down, PMOS current sources out through CP
OUT
and
NMOS current sinks in through CP
OUT+
, which decreases the
(CP
OUT+
, CP
OUT
) differential voltage. The charge pump up/
down matching is improved by an order of magnitude over the
conventional single-ended charge pump that depended on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS and
an NMOS matches an NMOS.
0
V
BIAS
P
P
P
N
N
UP
DOWN
DOWN
UP
V
BIAS
N
CP
OUT+
C
POUT–
Figure 24. Differential Charge Pump Cell with External Loop Filter Components
Fast Lock Timeout Counters
Timeout counters, clocked at one quarter the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). Whenever a new frequency is
programmed, the fast lock timers start and the PLL locks into
wide BW mode with the 64 identical 100 μA charge pump cells
active (6.4 mA total). When the ICP counter times out, the
charge pump current is reduced to 1× by deselecting cells in
binary steps over the next six timer clock cycles, until just one
100 μA cell is active. The charge pump current switching from
6.4 mA to 100 μA equates to an 8-to-1 change in loop band-
width. The loop filter must be changed to ensure stability when
this happens. That is the job of the SW1, SW2, and SW3 switches.
The application circuit (shown in Figure 36) shows how they
can be used to reconfigure the loop filter time constants. The
application circuits close to short out external loop filter resistors
during fast lock and open when their counters time out to restore
the filter time constants to their normal values for the 100 μA
charge pump current. Because it takes six timer clock cycles to
reduce the charge pump current to 1×, it is recommended that
both switch timers be programmed to the value of the ICP
timer + 7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4193BCPZ-RL | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| ADF4193BCPZ-RL7 | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| ADF4207BRU | Dual RF PLL Frequency Synthesizers |
| ADF4208BRU | Dual RF PLL Frequency Synthesizers |
| ADF4206 | Dual RF PLL Frequency Synthesizers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4193BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4193BCPZ-RL7 | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4193SP1BCPZ | 制造商:Analog Devices 功能描述: |
| ADF4193SP1BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193SP2BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。