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參數(shù)資料
| 型號： | ADF4193BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 437K |
| 代理商： | ADF4193BCPZ |
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ADF4193
INTERFACING
The ADF4193 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that have been clocked
into the input register on each rising edge of CLK are latched
into the appropriate register. See Figure 2 for the timing
diagram and Table 5 for the register address table.
Rev. B | Page 27 of 28
The maximum allowable serial clock rate is 33 MHz.
ADuC812 Interface
Figure 37 shows the interface between the ADF4193 and the
ADuC812
MicroConverter. Because the
ADuC812
is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Some registers of the ADF4193
require a 24-bit programming word. This is accomplished by
writing three 8-bit bytes from the MicroConverter to the device.
When the third byte is written, the LE input should be brought
high to complete the transfer.
An I/O port line on the
ADuC812
can also be used to detect
lock (MUX
OUT
configured as lock detect and polled by the
port input).
ADuC812
ADF4193
SCLOCK
CLK
DATA
LE
MUX
(LOCK DETECT)
MOSI
I/O PORTS
0
Figure 37. ADuC812 to ADF4193 Interface
ADSP-21xx Interface
Figure 38 shows the interface between the ADF4193 and the
ADSP-21xx digital signal processor. The ADF4193 needs a
24-bit serial word for some writes. The easiest way to accom-
plish this using the ADSP-21xx family is to use the autobuffered
transmit mode of operation with alternate framing. This
provides a means for transmitting an entire block of serial data
before an interrupt is generated. Set up the word length for
eight bits and use three memory locations for each 24-bit word.
To program each 24-bit word, store the three 8-bit bytes, enable
the autobuffered mode, and then write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
ADSP-21xx
ADF4193
SCLK
CLK
DATA
LE
MUX
(LOCK DETECT)
DT
TFS
I/O FLAGS
0
Figure 38. ADSP-21xx to ADF4193 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-3) are rectangular.
The printed circuit board (PCB) pad for these should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The land should be centered on
the pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with one ounce copper to plug
the via.
The user should connect the PCB thermal pad to A
GND
.
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| ADF4193BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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| ADF4193SP1BCPZ | 制造商:Analog Devices 功能描述: |
| ADF4193SP1BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
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