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參數(shù)資料
| 型號： | ADF4193BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 437K |
| 代理商： | ADF4193BCPZ |
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ADF4193
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the refer-
ence where the difference frequency can be inside the loop
bandwidth, thus the name integer boundary spurs.
Rev. B | Page 23 of 28
The 8:1 loop bandwidth switching ratio of the ADF4193 makes
it possible to attenuate all spurs to sufficiently low levels for
most applications. The final loop BW can be chosen to ensure
that all spurs are far enough out of band while meeting the lock
time requirements with the 8× bandwidth boost.
The ADF4193’s programmable modulus and R divider can also
be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers as the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise out through the RF
IN
pin back to the VCO,
resulting in reference spur levels as high as –90 dBc. These
spurs can be suppressed below –110 dBc by inserting sufficient
reverse isolation, for example, through an RF buffer between
the VCO and RF
IN
pin. In addition, care should be taken in the
PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
POWER-UP INITIALIZATION
After applying power to the ADF4193, a 14-step sequence is
recommended, as described in Table 8.
The divider and timer setting used in the example in Table 8 is
for a DCS1800 Tx synthesizer with a 104 MHz REF
IN
frequency.
Table 8. Power-Up Initialization Sequence
Register
Bits
Codes
1
R5 [7:0]
FD
2
R3 [15:0]
005B
Step
Hex
Description
Set all power-down bits.
PD polarity = 1, ground CP
OUT+
/
CP
OUT
–.
Allow time for loop filter
capacitors to discharge.
Clear test modes.
Initialize PLL modes, digital lock
detect on MUX
OUT
.
10 ns lock detect threshold,
digital lock detect on MUX
OUT
.
SW1/SW2 timer = 10.8 μs.
SW3 timer = 10.8 μs.
ICP timer = 8.6 μs.
Phase = 26.
8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
PD polarity = 1, release CP
OUT
+/
CP
OUT
–.
Clear all power-down bits.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
Wait
10 ms
3
4
R7 [15:0]
R6 [15:0]
0007
000E
5
R6 [15:0]
900E
6
7
8
9
10
R4 [23:0]
R4 [23:0]
R4 [23:0]
R2 [15:0]
R1 [23:0]
004464
00446C
004394
00D2
520209
11
R0 [23:0]
480140
12
R3 [15:0]
007B
13
14
R5 [7:0]
R0 [23:0]
05
480140
The ADF4193 powers up after Step 13. It locks to the
programmed channel frequency after Step 14.
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOK-UP TABLE
Once the ADF4193 is initialized, a write to Register R0 is all
that is required to program a new output frequency. The N
divider is updated with the values of INT and FRAC on the next
PFD cycle following the LE edge that latches in the R0 word.
However, the settling time and spurious performance of the
synthesizer can be further optimized by modifying R1 and R2
register settings on a channel-by-channel basis. These settings
are double buffered by the write to R0. This means that while
the data is loaded in through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not
updated with their data until the next write to Register R0.
The R2 register can be used to digitally adjust the phase of the
VCO output relative to the reference edge. The phase can be
adjusted over the full 360° range at RF with a resolution of
360°/MOD. In most frequency synthesizer applications, the
actual phase offset of the VCO output with respect to the
reference is unknown and does not matter. In such applications,
the phase adjustment capability of the R2 register can instead be
used to optimize the settling time performance, as described in
the Phase Look-Up Table section.
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