- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9088 > ADF4351BCPZ-RL7 (Analog Devices Inc)IC SYNTH PLL VCO 32LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADF4351BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時(shí)鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Data Sheet
ADF4351
Rev. 0 | Page 19 of 28
Reference Doubler
Setting the DB25 bit to 0 disables the doubler and feeds the REFIN
signal directly into the 10-bit R counter. Setting this bit to 1 multi-
plies the REFIN frequency by a factor of 2 before feeding it into
the 10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
When the doubler is enabled and the low spur mode is selected,
the in-band phase noise performance is sensitive to the REFIN duty
cycle. The phase noise degradation can be as much as 5 dB for
REFIN duty cycles outside a 45% to 55% range. The phase noise
is insensitive to the REFIN duty cycle in the low noise mode and
when the doubler is disabled.
The maximum allowable REFIN frequency when the doubler is
enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD, which extends the maximum
REFIN input rate. This function allows a 50% duty cycle signal to
appear at the PFD input, which is necessary for cycle slip reduction.
10-Bit R Counter
The 10-bit R counter (Bits[DB23:DB14]) allows the input reference
frequency (REFIN) to be divided down to produce the reference
clock to the PFD. Division ratios from 1 to 1023 are allowed.
Double Buffer
The DB13 bit enables or disables double buffering of
Bits[DB22:DB20] in Register 4. For information about how
double buffering works, see the Program Modes section.
Charge Pump Current Setting
Bits[DB12:DB9] set the charge pump current. This value should
be set to the charge pump current that the loop filter is designed
with (see Figure 26).
Lock Detect Function (LDF)
The DB8 bit configures the lock detect function (LDF). The LDF
controls the number of PFD cycles monitored by the lock detect
circuit to ascertain whether lock has been achieved. When DB8 is
set to 0, the number of PFD cycles monitored is 40. When DB8
is set to 1, the number of PFD cycles monitored is 5. It is recom-
mended that the DB8 bit be set to 0 for fractional-N mode and
to 1 for integer-N mode.
Lock Detect Precision (LDP)
The lock detect precision bit (Bit DB7) sets the comparison
window in the lock detect circuit. When DB7 is set to 0, the
comparison window is 10 ns; when DB7 is set to 1, the window
is 6 ns. The lock detect circuit goes high when n consecutive
PFD cycles are less than the comparison window value; n is set
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,
40 consecutive PFD cycles of 10 ns or less must occur before
digital lock detect goes high.
For fractional-N applications, the recommended setting for
Bits[DB8:DB7] is 00; for integer-N applications, the recom-
mended setting for Bits[DB8:DB7] is 11.
Phase Detector Polarity
The DB6 bit sets the phase detector polarity. When a passive
loop filter or a noninverting active loop filter is used, this bit
should be set to 1. If an active filter with an inverting charac-
teristic is used, this bit should be set to 0.
Power-Down (PD)
The DB5 bit provides the programmable power-down mode.
Setting this bit to 1 performs a power-down. Setting this bit to 0
returns the synthesizer to normal operation. In software power-
down mode, the part retains all information in its registers. The
register contents are lost only if the supply voltages are removed.
When power-down is activated, the following events occur:
Synthesizer counters are forced to their load state conditions.
VCO is powered down.
Charge pump is forced into three-state mode.
Digital lock detect circuitry is reset.
RFOUT buffers are disabled.
Input registers remain active and capable of loading and
latching data.
Charge Pump Three-State
Setting the DB4 bit to 1 puts the charge pump into three-state
mode. This bit should be set to 0 for normal operation.
Counter Reset
The DB3 bit is the reset bit for the R counter and the N counter
of the ADF4351. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal opera-
tion, this bit should be set to 0.
REGISTER 3
Control Bits
When Bits[C3:C1] are set to 011, Register 3 is programmed.
Figure 27 shows the input data format for programming this
register.
Band Select Clock Mode
Setting the DB23 bit to 1 selects a faster logic sequence of band
selection, which is suitable for high PFD frequencies and is
necessary for fast lock applications. Setting the DB23 bit to 0 is
recommended for low PFD (<125 kHz) values. For the faster
band select logic modes (DB23 set to 1), the value of the band
select clock divider must be less than or equal to 254.
Antibacklash Pulse Width (ABP)
Bit DB22 sets the PFD antibacklash pulse width. When Bit DB22
is set to 0, the PFD antibacklash pulse width is 6 ns. This setting is
recommended for fractional-N use. When Bit DB22 is set to 1,
the PFD antibacklash pulse width is 3 ns, which results in phase
noise and spur improvements in integer-N operation. For
fractional-N operation, the 3 ns setting is not recommended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V24A24H300BF2 | CONVERTER MOD DC/DC 24V 300W |
| M83723/95R10057 | CONN PLUG 5POS STRAIGHT W/SCKT |
| V24A15H300BL | CONVERTER MOD DC/DC 15V 300W |
| D38999/20JC4JN | CONN RCPT 4POS WALL MNT W/SCKT |
| MS27474E16B6SD | CONN RCPT 6POS JAM NUT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4351BCPZ-U5 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4351BCPZ-U6 | 制造商:Analog Devices 功能描述:WIDEBAND SYNTHESIZER WITH INTEGRATED VCO - Rail/Tube |
| ADF4355-2BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4355-2BCPZ-RL7 | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1,500 |
| ADF4355-3BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1：3 差分 - 輸入:輸出:是/是 頻率 - 最大值:6.6GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。