V
參數(shù)資料
型號： ADF4351BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 26/28頁
文件大小： 0K
描述： IC SYNTH PLL VCO 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時(shí)鐘/頻率合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 4.4GHz
除法器/乘法器： 是/是
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP（5x5）
包裝： 帶卷 (TR)
Data Sheet
ADF4351
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
2
DATA
3
LE
4
CE
5
SW
6
7
24
VREF
23
VCOM
22
21
20
19
18
17
8
S
DV
DD
ADF4351
TOP VIEW
(Not to Scale)
9
AG
ND
10
AV
DD
11
RE
F
IN
12
DG
ND
13
DV
DD
14
15
16
32
31
30
29
28
SD
G
ND
27
26
25
PIN 1
INDICATOR
VP
CPOUT
CPGND
M
UX
O
UT
RSET
RF
O
UT
A+
RF
O
UT
B+
RF
O
UT
B
RF
O
UT
A
V
CO
VTUNE
AGNDVCO
TEMP
P
DB
RF
LD
A
G
NDV
CO
VVCO
NOTES
1. THE LFCSP HAS AN EXPOSED PAD THAT
MUST BE CONNECTED TO GND.
09800-
003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3
LE
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is
selected by the three control bits. This input is a high impedance CMOS input.
4
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device, depending on the status of the power-down bits.
5
SW
Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode.
6
V
P
Charge Pump Power Supply. V
P must have the same value as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
7
CP
OUT
Charge Pump Output. When enabled, this output provides ±I
CP to the external loop filter. The output of the
loop filter is connected to V
TUNE to drive the internal VCO.
8
CP
GND
Charge Pump Ground. This output is the ground return pin for CP
OUT.
9
AGND
Analog Ground. Ground return pin for AV
DD.
10
AV
DD
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground
plane as close to this pin as possible. AV
DD must have the same value as DVDD.
11, 18, 21
A
GNDVCO
VCO Analog Ground. Ground return pins for the VCO.
12
RF
OUTA+
VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is
available.
13
RF
OUTA
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided-
down version is available.
14
RF
OUTB+
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down
version is available.
15
RF
OUTB
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided-down version is available.
16, 17
V
VCO
Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog
ground plane as close to these pins as possible. V
VCO must have the same value as AVDD.
19
TEMP
Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as
possible.
20
V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
OUT
output voltage.
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