- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9088 > ADF4351BCPZ-RL7 (Analog Devices Inc)IC SYNTH PLL VCO 32LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADF4351BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時(shí)鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Data Sheet
ADF4351
Rev. 0 | Page 21 of 28
RF SYNTHESIZER—A WORKED EXAMPLE
The following equations are used to program the ADF4351
synthesizer:
RFOUT = [INT + (FRAC/MOD)] × (fPFD/RF Divider)
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the numerator of the fractional division (0 to MOD 1).
MOD is the preset fractional modulus (2 to 4095).
RF Divider is the output divider that divides down the
VCO frequency.
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit (0 or 1).
R is the RF reference division factor (1 to 1023).
T is the reference divide-by-2 bit (0 or 1).
As an example, a UMTS system requires a 2112.6 MHz RF
frequency output (RFOUT); a 10 MHz reference frequency input
(REFIN) is available and a 200 kHz channel resolution (fRESOUT) is
required on the RF output.
Note that the ADF4351 VCO operates in the frequency range
of 2.2 GHz to 4.4 GHz. Therefore, the RF divider of 2 should be
used (VCO frequency = 4225.2 MHz, RFOUT = VCO frequency/
RF divider = 4225.2 MHz/2 = 2112.6 MHz).
It is also important where the loop is closed. In this example,
the loop is closed before the output divider (see Figure 30).
fPFD
PFD
VCO
N
DIVIDER
÷2
RFOUT
09800-
027
Figure 30. Loop Closed Before Output Divider
Channel resolution (fRESOUT) of 200 kHz is required at the output
of the RF divider. Therefore, the channel resolution at the output
of the VCO (fRES) needs to be 2 × fRESOUT, that is, 400 kHz.
MOD = REFIN/fRES
MOD = 10 MHz/400 kHz = 25
From Equation 4,
fPFD = [10 MHz × (1 + 0)/1] = 10 MHz
(5)
2112.6 MHz = 10 MHz × [(INT + (FRAC/25))/2]
(6)
where:
INT = 422.
FRAC = 13.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. Doubling the reference signal doubles the PFD
comparison frequency, which improves the noise performance of
the system. Doubling the PFD frequency usually improves noise
performance by 3 dB. Note that in fractional-N mode, the PFD
cannot operate above 32 MHz due to a limitation in the speed
of the Σ-Δ circuit of the N divider. For integer-N applications,
the PFD can operate up to 90 MHz.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. For more information, see the Cycle Slip Reduction
for Faster Lock Times section.
12-BIT PROGRAMMABLE MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at the
RF output. For example, a GSM system with 13 MHz REFIN sets
the modulus to 65. This means that the RF output resolution
(fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With
dither off, the fractional spur interval depends on the selected
modulus values (see Table 7).
Unlike most other fractional-N PLLs, the ADF4351 allows the
user to program the modulus over a 12-bit range. When com-
bined with the reference doubler and the 10-bit R counter, the
12-bit modulus allows the user to set up the part in many
different configurations for the application.
For example, consider an application that requires a 1.75 GHz
RF frequency output with a 200 kHz channel step resolution.
The system has a 13 MHz reference signal.
One possible setup is to feed the 13 MHz reference signal
directly into the PFD and to program the modulus to divide
by 65. This results in the required 200 kHz resolution.
Another possible setup is to use the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz is then fed
into the PFD, and the modulus is programmed to divide by 130.
This setup also results in 200 kHz resolution but offers superior
phase noise performance over the first setup.
The programmable modulus is also very useful for multi-
standard applications. For example, if a dual-mode phone
requires PDC and GSM 1800 standards, the programmable
modulus is of great benefit.
PDC requires 25 kHz channel step resolution, whereas GSM 1800
requires 200 kHz channel step resolution. A 13 MHz reference
signal can be fed directly to the PFD, and the modulus can be
programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz).
The modulus must be reprogrammed to 65 for GSM 1800 opera-
tion (13 MHz/65 = 200 kHz).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V24A24H300BF2 | CONVERTER MOD DC/DC 24V 300W |
| M83723/95R10057 | CONN PLUG 5POS STRAIGHT W/SCKT |
| V24A15H300BL | CONVERTER MOD DC/DC 15V 300W |
| D38999/20JC4JN | CONN RCPT 4POS WALL MNT W/SCKT |
| MS27474E16B6SD | CONN RCPT 6POS JAM NUT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4351BCPZ-U5 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4351BCPZ-U6 | 制造商:Analog Devices 功能描述:WIDEBAND SYNTHESIZER WITH INTEGRATED VCO - Rail/Tube |
| ADF4355-2BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4355-2BCPZ-RL7 | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1,500 |
| ADF4355-3BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1：3 差分 - 輸入:輸出:是/是 頻率 - 最大值:6.6GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。