
ADMtek Inc.
V1.0
3.3
Switch Register Map......................................................................................3-42
3.3.1
Version ID (Offset: 0h)..........................................................................3-42
3.3.2
Link Status (Offset: 1h)..........................................................................3-42
3.3.3
Speed Status (Offset: 2h)........................................................................3-43
3.3.4
Duplex Status (Offset: 3h)......................................................................3-44
3.3.5
Flow Control Status (Offset: 4h)............................................................3-44
3.3.6
Address Table Control and Status Register...........................................3-45
3.3.7
PHY Control Register (Offset: bh).........................................................3-51
3.3.8
Hardware Status (Offset: dh).................................................................3-51
3.3.9
Receive Packet Count Overflow (Offset: eh).........................................3-52
3.3.10
Receive Packet Length Count Overflow (Offset: fh)..............................3-53
3.3.11
Transmit Packet Count Overflow (Offset: 10h).....................................3-53
3.3.12
Transmit Packet Length Count Overflow (Offset: 11h).........................3-54
3.3.13
Error Count Overflow (Offset: 12h)......................................................3-54
3.3.14
Collision Count Overflow (Offset: 13h).................................................3-55
3.3.15
Renew Counter Register (Offset: 14h)...................................................3-56
3.3.16
Read Counter Control & Status Register ..............................................3-57
3.3.17
Reload MDIO Register (Offset: 17h).....................................................3-57
3.3.18
Spanning Tree Port State 0 (Offset: 18h) ..............................................3-58
3.3.19
Spanning Tree Port State 1 (Offset: 19h) ..............................................3-58
3.3.20
Source Port Register (Offset: 1ah) ........................................................3-59
3.3.21
Transmit Port Register (Offset: 1bh).....................................................3-59
3.3.22
Counter Register: Offset Hex. 0100h ~ 019b.........................................3-59
Chapter 4 Electrical Specification................................................................................4-1
4.1
DC Characterization.........................................................................................4-1
4.1.1
Absolute Maximum Rating.......................................................................4-1
4.1.2
Recommended Operating Conditions......................................................4-1
4.1.3
DC Electrical Characteristics for 3.3V Operation..................................4-1
4.2
AC Characterization.........................................................................................4-2
4.2.1
XI/OSCI (Crystal/Oscillator) Timing.......................................................4-2
4.2.1
Power On Reset........................................................................................4-2
4.2.2
EEPROM Interface Timing......................................................................4-3
4.2.3
10Base-TX MII Output Timing................................................................4-3
4.2.4
10Base-TX MII Input Timing...................................................................4-4
4.2.5
100Base-TX MII Output Timing..............................................................4-5
4.2.6
100Base-TX MII Input Timing.................................................................4-5
4.2.7
Reduced MII Timing ................................................................................4-6
4.2.8
SS_SMII Transmit Timing........................................................................4-7
4.2.9
SS_SMII Receive Timing..........................................................................4-7
4.2.10
Serial Management Interface (MDC/MDIO) Timing..............................4-8
Chapter 5 Packaging......................................................................................................5-1
ADM6926
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