參數(shù)資料
型號： ADSP-21061LKB-160
廠商： Analog Devices Inc
文件頁數(shù)： 19/52頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 225BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點
接口： 同步串行端口（SSP）
時鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BBGA
供應(yīng)商設(shè)備封裝： 225-PBGA
包裝： 托盤
Rev. D | Page 26 of 52 | May 2013
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Bus Master on Page 25). When accessing a slave ADSP-21061,
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on Page 28). The slave ADSP-21061
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Table 14. Synchronous Read/Write—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSSDATI
Data Setup Before CLKIN
(50 MHz, tCK = 20 ns)1
2 + DT/8
1.5 + DT/8
ns
tHSDATI
Data Hold After CLKIN
3.5 – DT/8
ns
tDAAK
ACK Delay After Address, Selects2, 3
15 + 7DT/8 + W
ns
tSACKC
ACK Setup Before CLKIN3
6.5+DT/4
ns
tHACK
ACK Hold After CLKIN
–1 – DT/4
ns
Switching Characteristics
tDADRO
Address, MSx, BMS, SW Delay After CLKIN2
6.5 – DT/8
ns
tHADRO
Address, MSx, BMS, SW Hold After CLKIN
–1 – DT/8
ns
tDPGC
PAGE Delay After CLKIN
9 + DT/8
16 + DT/8
ns
tDRDO
RD High Delay After CLKIN
–1.5 – DT/8
4 – DT/8
ns
tDWRO
WR High Delay After CLKIN
(50 MHz, tCK = 20 ns)
–2.5 – 3DT/16
–1.5 – 3DT/16
4 – 3DT/16
ns
tDRWL
RD/WR Low Delay After CLKIN
8 + DT/4
12 + DT/4
ns
tSDDATO
Data Delay After CLKIN
19 + 5DT/16
ns
tDATTR
Data Disable After CLKIN4
0 – DT/8
7 – DT/8
ns
tDADCCK
ADRCLK Delay After CLKIN
4 + DT/8
10 + DT/8
ns
tADRCK
ADRCLK Period
tCK
ns
tADRCKH
ADRCLK Width High
(tCK/2 – 2)
ns
tADRCKL
ADRCLK Width Low
(tCK/2 – 2)
ns
1 This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK < 25 ns. For all other devices, use the preceding timing specification of the same name.
2 The falling edge of MSx, SW, BMS is referenced.
3 ACK delay/setup: User must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(high).
4 See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
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