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參數資料
| 型號： | ADSP-2183KCAZ-210 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 23/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 52MHZ 144-BGA |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 52MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應商設備封裝： | 144-迷你型BGA |
| 包裝： | 托盤 |
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ADSP-2183
–3–
REV. C
In addition to the address and data bus for external memory
connection, the ADSP-2183 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (
BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2183 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
The ADSP-2183 can respond to thirteen possible interrupts,
eleven of which are accessible at any given time. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2183 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2183 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2183
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals, internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
OUTPUT REGS
ALU
OUTPUT REGS
MAC
TIMER
INPUT REGS
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PMA BUS
DMA BUS
PMD BUS
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
BUS
EXCHANGE
DMD BUS
PROGRAM
SRAM
16k 24
DATA
SRAM
16k 16
BYTE
DMA
CONTROLLER
MUX
14
24
16
DMD
BUS
PMA BUS
DMA BUS
PMD BUS
INPUT REGS
SHIFTER
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
INPUT REGS
ALU
OUTPUT REGS
R BUS
16
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
COMPANDING
CIRCUITRY
5
INTERNAL
DMA
PORT
INTERRUPTS
POWER
DOWN
CONTROL
LOGIC
2
8
3
MUX
PROGRAMMABLE
I/O
FLAGS
14
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
16
4
24
ADSP-2183 INTEGRATION
21xx CORE
Figure 1. Block Diagram
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| ADSP2183KS133 | 制造商:AD 功能描述:* |
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| ADSP-2183KST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3.3V 16BITDSP,33MIPS,16KWRDSPM/DM,128TQF - Bulk |
| ADSP-2183KST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3.3V,16BITDSP,40MIPS,16KWRDSPM/DM,128TQF - Bulk |
| ADSP-2183KST-210 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 52MHz 52MIPS 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3.3V 16BITDSP,52MIPS,16KWORDSPM/DM,128TQ - Bulk 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
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