參數(shù)資料
型號(hào)： ADSP-2185NKCAZ-320
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 80MHZ 144CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 80kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.80V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-CSBGA（10x10）
包裝： 托盤
ADSP-218xN
Rev. A
|
Page 25 of 48
|
August 2006
ENVIRONMENTAL CONDITIONS
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in Figure 20. The time is the interval from when a refer-
ence signal reaches a high or low voltage level to when the
output voltages have changed by 0.5 V from the measured out-
put high or low voltage.
The decay time, tDECAY, is dependent on the capacitive load, CL,
and the current load, iL, on the output pin. It can be approxi-
mated by the following equation:
from which
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 20. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Table 14. Thermal Resistance
Rating Description
1
1 Where the Ambient Temperature Rating (TAMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
Symbol
LQFP
(
°C/W)
BGA
(
°C/W)
Thermal Resistance (Case-
to-Ambient)
θ
CA
48
63.3
Thermal Resistance
(Junction-to-Ambient)
θ
JA
50
70.7
Thermal Resistance
(Junction-to-Case)
θ
JC
27.4
Figure 18. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Figure 19. Equivalent Loading for AC Measurements (Including All Fixtures)
1.5V
OUTPUT
INPUT
1.5V
2.0V
0.8V
TO
OUTPUT
PIN
50pF
1.5V
I
OH
IOL
Figure 20. Output Enable/Disable
2.0V
1.0V
tENA
REFERENCE
SIGNAL
OUTPUT
tDECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
tDIS
tMEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) + 0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
tDECAY
CL 0.5V
×
iL
------------------------
=
tDIS
tMEASURED tDECAY
–
=
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