參數(shù)資料
型號: ADSP-2185NKCAZ-320
廠商: Analog Devices Inc
文件頁數(shù): 24/48頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 80MHZ 144CSPBGA
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 80MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.80V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 144-CSBGA(10x10)
包裝: 托盤
Rev. A
|
Page 30 of 48
|
August 2006
ADSP-218xN
Bus Request–Bus Grant
Table 17. Bus Request–Bus Grant
Parameter
Min
Max
Unit
Timing Requirements:
tBH
BR Hold after CLKOUT High1
1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
0.25tCK + 2
ns
tBS
BR Setup before CLKOUT Low1
0.25tCK + 8
ns
Switching Characteristics:
tSD
CLKOUT High to xMS, RD, WR Disable
2
2 xMS = PMS, DMS, CMS, IOMS, BMS.
0.25tCK + 8
ns
tSDB
xMS, RD, WR Disable to BG Low
0
ns
tSE
BG High to xMS, RD, WR Enable
0
ns
tSEC
xMS, RD, WR Enable to CLKOUT High
0.25tCK – 3
ns
tSDBH
xMS, RD, WR Disable to BGH Low3
3 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
0ns
tSEH
BGH High to xMS, RD, WR Enable3
0ns
Figure 28. Bus Request–Bus Grant
CLKOUT
tSD
tSDB
tSE
tSEC
t
SDBH
tSEH
tBS
BR
tBH
CLKOUT
PMS, DMS
BMS, RD
CMS, WR,
IOMS
BG
BGH
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