DIS is the difference between tMEASURE" />
參數(shù)資料
型號(hào)： ADSP-2191MBCAZ-140
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SPI，SSP，UART
時(shí)鐘速率： 140MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 3.00V，3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤
–41–
REV. A
ADSP-2191M
The output disable time t
DIS is the difference between tMEASURED
and t
DECAY as shown in Figure 26. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays –V from the measured output high or
output low voltage. The t
DECAY is calculated with test loads CL
and I
L, and with – V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 26). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY using the equation at Output Disable Time
on Page 40. Choose –V to be the difference between the
ADSP-2191M’s output voltage and the input threshold for the
device requiring the hold time. A typical –V will be 0.4 V. C
L is
the total bus capacitance (per data line), and I
L is the total leakage
or three-state current (per data line). The hold time will be t
DECAY
plus the minimum disable time (i.e., t
DATRWH for the
write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF. Figure 28 and Figure 29
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see Output Disable Time on Page 40.) The
graphs in these figures may not be linear outside the ranges
shown.
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Thermal Characteristics
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T
AMB) as calculated using the
formula below.
Figure 26. Output Enable/Disable
Figure 27. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 28. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
t
DECAY
C
L V
I
L
---------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V2.0V
VOL (MEASURED) + V1.0V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
INPUT
OR
OUTPUT
1.5V
Figure 29. Typical Output Rise Time (10%-90%,
VDDEXT = Minimum at Maximum Ambient Operating
Temperature) vs. Load Capacitance
40
0
30
20
10
LOAD CAPACITANCE – pF
0250
50
100
150
200
R
IS
E
A
N
D
F
A
L
T
IM
E
S
–
n
s
(1
0
%
–
9
0
%
)
FALL TIME
RISE TIME
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