參數(shù)資料
型號: ADSP-BF512BBCZ-4F4
廠商: Analog Devices Inc
文件頁數(shù): 20/68頁
文件大?。?/td> 0K
描述: IC DSP 16/32B 400MHZ 168CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: I²C,PPI,SPI,SPORT,UART/USART
時鐘速率: 400MHz
非易失內(nèi)存: 閃存(4Mb)
芯片上RAM: 116kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 168-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 168-CSPBGA(12x12)
包裝: 托盤
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 27 of 68
|
January 2011
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 23 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 9 , Table 10,
and Table 11 on Page 21, combinations of CLKIN and clock
multipliers must not select core/peripheral clocks in excess of
the processor’s speed grade.
Table 23. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12
50
MHz
fCKIN
CLKIN Frequency (Automotive Models)1, 2, 3, 4
14
50
MHz
tCKINL
CLKIN Low Pulse1
10
ns
tCKINH
CLKIN High Pulse
10
ns
tWRST
RESET Asserted Pulse Width Low
5
11 × tCKIN
ns
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF Delay
11
ns
1 Applies to PLL bypass mode and PLL nonbypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11 on Page 21.
3 The t
CKIN period (see Figure 7) equals 1/fCKIN.
4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5 Applies after power-up sequence is complete. See Table 24 and Figure 8 for power-up reset timing.
Figure 7. Clock and Reset Timing
Table 24. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RESET Deasserted after the V
DDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are
Stable and Within Specification
3500 × tCKIN
ns
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
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