參數(shù)資料
型號(hào): ADT7463
廠商: Analog Devices, Inc.
英文描述: dB COOL Remote Thermal Controller and Voltage Monitor
中文描述: 分貝超酷的遠(yuǎn)程熱控制器和電壓監(jiān)視器
文件頁(yè)數(shù): 11/53頁(yè)
文件大?。?/td> 719K
代理商: ADT7463
REV. 0
ADT7463
–11–
4. If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
ADT7463 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7463 are discussed below. The following abbreviations are
used in the diagrams:
S – START
P – STOP
R – READ
W – WRITE
A – ACKNOWLEDGE
A
– NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a STOP condition on SDA and the
transaction ends.
For the ADT7463, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
S
ASLAVE
A P
1
2
3
4
5
6
REGISTER
ADDRESS
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a STOP condition on SDA to end the
transaction.
This is illustrated in Figure 11.
S
ASLAVE
1
2
3
4
5
6
A DATA A P
7
8
REGISTER
ADDRESS
Figure 11. Single Byte Write to a Register
ADT7463 READ OPERATIONS
The ADT7463 uses the following SMBus read protocols:
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a STOP condition on SDA and the trans-
action ends.
In the ADT7463, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
S
SLAVE
ADDRESS
R
A
DATA
A
P
1
2
3
4
5
6
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert Response Address (ARA) is a feature of SMBus devices
that allows an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
The
SMBALERT
output can be used as an interrupt output or
can be used as an
SMBALERT
. One or more outputs can be
connected to a common
SMBALERT
line connected to the
master. If a device’s
SMBALERT
line goes low, the following
procedure occurs:
1.
SMBALERT
is pulled low.
2. Master initiates a read operation and sends the Alert
Response Address (ARA = 0001 100). This is a general
call address that must not be used as a specific device
address.
3. The device whose
SMBALERT
output is low responds to
the Alert Response Address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.
4. If more than one device’s
SMBALERT
output is low, the
one with the lowest device address will have priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7463 has responded to the Alert Response
Address, the master must read the Status Registers and the
SMBALERT
will only be cleared if the error condition has
gone away.
SMBUS TIMEOUT
The ADT7463 includes an SMBus Timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus Timeout feature, so it
can be disabled.
CONFIGURATION REGISTER 1 – Register 0x40
<6>
TODIS = 0;
SMBus Timeout ENABLED (default)
<6>
TODIS = 1;
SMBus Timeout DISABLED
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