參數(shù)資料
型號: ADT7463
廠商: Analog Devices, Inc.
英文描述: dB COOL Remote Thermal Controller and Voltage Monitor
中文描述: 分貝超酷的遠(yuǎn)程熱控制器和電壓監(jiān)視器
文件頁數(shù): 37/53頁
文件大?。?/td> 719K
代理商: ADT7463
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ADT7463
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Table XIV. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
<0>
Name
12 V
R/W
Read Only
Description
A one indicates the 12 V high or low limit has been exceeded. This bit gets cleared on a
read of the Status Register only if the error condition has subsided. If Pin 21 is config-
ured as VID5, this bit is the VID Change bit. This bit gets set when the levels on VID0–5
are different than they were 11
μ
s previously. This can be used to generate an
SMBALERT
whenever the VID code changes.
A one indicates that one of the
THERM
overtemperature limits has been
exceeded. This bit gets cleared on a read of the Status Register when the
temperature drops below
THERM
– T
HYST
.
A one indicates that Fan 1 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 1 output is off.
A one indicates that Fan 2 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 2 output is off.
A one indicates that Fan 3 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 3 output is off.
A one indicates that Fan 4 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 3 output is off.
If Pin 14 or Pin 20 is configured as the
THERM
timer input for
THERM
monitoring, then this bit gets set when the
THERM
assertion time exceeds the
limit programmed in the
THERM
Limit Register (Reg. 0x7A).
A one indicates either an open or short circuit on the Thermal Diode 1 inputs.
A one indicates either an open or short circuit on the Thermal Diode 2 inputs.
<1>
OVT
Read Only
<2>
FAN1
Read Only
<3>
FAN2
Read Only
<4>
FAN3
Read Only
<5>
F4P
Read Only
Read Only
<6>
<7>
D1
D2
Read Only
Read Only
Table XV. Register 43H – VID Register (Power-On Default = 0x00)
Bit
<4:0>
Name
VID[4:0]
R/W
Read Only
Description
The VID[4:0] inputs from the CPU to indicate the expected processor core voltage. On
power-up, these bits reflect the state of the VID Pins even if monitoring is not enabled.
<5>
VID5
Read Only
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always
reads back 0 (power-on default).
<6>
THLD
Read/Write
This selects the input switching threshold for the VID inputs. THLD = 0 selects
a
threshold of 1 V (V
OL
< 0.8 V, V
IH
> 1.7 V). THLD = 1 lowers the switching threshold
to 0.6 V (V
OL
< 0.4 V, V
IH
> 0.8 V).
<7>
VIDSEL
Read/Write
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
VIDSEL = 1 configures Pin 21 as the VID5 input. This also allows VID code
changes to be detected.
Table XVI. Voltage Limit Registers
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
2.5 V Low Limit
2.5 V High Limit
V
CCP
Low Limit
V
CCP
High Limit
V
CC
Low Limit
V
CC
High Limit
5 V Low Limit
5 V High Limit
12 V Low Limit
12 V High Limit
Power-On Default
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Setting the Configuration Register 1 Lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit (
comparison).
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