
REV. 0
–14–
ADT7463
VIC CODE MONITORING
The ADT7463 has five dedicated Voltage ID (VID Code)
inputs. These are digital inputs that can be read back through
the VID Register (Reg. 0x43) to determine the Processor Volt-
age required/being used in the system. Five VID Code inputs
support VRM9.x solutions. In addition, Pin 21 (12 V input) can
be reconfigured as a sixth VID input to satisfy future VRM
requirements.
VID CODE REGISTER – Register 0x43
<0> = VID0
(reflects logic state of Pin 5)
<1> = VID1
(reflects logic state of Pin 6)
<2> = VID2
(reflects logic state of Pin 7)
<3> = VID3
(reflects logic state of Pin 8)
<4> = VID4
(reflects logic state of Pin 19)
<5> = VID5
(Reconfigurable 12 V input). This bit reads 0
when Pin 21 is configured as the 12 V input. This bit reflects
the logic state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID Code inputs is approxi-
mately 1 V. To enable future compatibility, it is possible to
reduce the VID Code input threshold to 0.6 V. Bit 6
(THLD) of VID Register (Reg. 0x43) controls the VID input
threshold voltage.
VID CODE REGISTER – Register 0x43
<6> THLD = 0;
VID Switching Threshold = 1 V,
V
OL
< 0.8V, V
IH
> 1.7 V, V
MAX
= 3.3 V
THLD = 1;
VID Switching Threshold = 0.6 V
V
OL
< 0.4 V, V
IH
> 0.8 V, V
MAX
= 3.3 V
RECONFIGURING PIN 21 (12V/VID5) AS VID5 INPUT
Pin 21 can be reconfigured as a sixth VID Code input (VID5)
for VRM10 compatible systems. Since the pin is configured as
VID5, it will no longer be possible to monitor a 12 V supply.
Bit 7 of the VID Register (Reg. 0x43) determines the function
of Pin 21. System or BIOS software can read the state of Bit 7
to determine whether the system is designed to monitor 12 V or
is monitoring a sixth VID input.
VID CODE REGISTER – Register 0x43
<7> VIDSEL = 0;
Pin 21 functions as 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1;
Pin 21 functions as the sixth VID Code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID Code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7463 has a VID Code change detect function. When
Pin 21 is configured as the VID5 input, VID Code changes can
be detected and reported back by the ADT7463. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12V/VC bit and denotes a VID
change when set. The VID Code Change bit gets set when the
logic states on the VID inputs are different than they were 11
μ
s
previously. The change of VID code can be used to generate
an
SMBALERT
interrupt. If an
SMBALERT
interrupt is not
required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75)
when set, will prevent
SMBALERT
s from occurring on VID
code changes.
STATUS REGISTER 2 – Register 0x42
<0> 12V/VC = 0;
If Pin 21 is configured as VID5, then a
logic 0 denotes no change in VID Code within last 11
μ
s.
<0> 12V/VC = 1;
If Pin 21 is configured as VID5, then a logic
1 means that a change has occurred on the VID Code inputs
within the last 11
μ
s. An
SMBALERT
will be generated if this
function is enabled.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility:
Turn Off Averaging
For each voltage measurement read from a value register, 16
readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This effectively gives a reading 16 times faster
(711
μ
s) but the reading may be noisier.
Bypass Voltage Input Attenuators
Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes
the attenuation circuitry from the 2.5 V, V
CCP
, V
CC
, 5 V, and
12 V inputs. This allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into Single-Channel ADC Conversion Mode. In this
mode, the ADT7463 can be made to read a single voltage chan-
nel only. If the internal ADT7463 clock is used, the selected
input will be read every 711
μ
s. The appropriate ADC Channel
is selected by writing to Bits <7:5> of the TACH1 Minimum
High Byte Register (0x55).
Bits <7:5> Reg 0x55
000
001
010
011
100
Channel Selected
2.5 V
V
CCP
V
CC
5 V
12 V
Configuration Register 2 (Reg. 0x73)
<4> = 1
Averaging Off
<5> = 1
Bypass Input Attenuators
<6> = 1
Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5>
Selects ADC Channel for Single-Channel Convert Mode