參數(shù)資料
型號(hào)： ADUC7023BCPZ62I-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 53/96頁(yè)
文件大?。?/td> 0K
描述： IC MCU 12BIT 62KB FLASH 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 12
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7023
| Page 57 of 96
Table 64. SPICON MMR Bit Designations
Bit
Name
Description
15 to
14
SPIMDE
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have
been received into the FIFO.
[11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full or four bytes
present.
13
SPITFLH
SPI Tx FIFO flush enable bit.
This bit is set to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
This bit is cleared to disable Tx FIFO flushing.
12
SPIRFLH
SPI Rx FIFO flush enable bit.
This bit is set to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set, all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
This bit is cleared to disable Rx FIFO flushing.
11
SPICONT
Continuous transfer enable.
This bit is set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the Tx register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.
This bit is cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.
10
SPILP
Loop back enable bit.
This bit is set by the user to connect MISO to MOSI and test software.
This bit is cleared by the user to be in normal mode.
9
SPIOEN
Slave MISO output enable bit.
This bit is set for MISO to operate as normal.
This bit is cleared to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.
8
SPIROW
SPIRX overflow overwrite enable.
This bit is set by the user; the valid data in the Rx register is overwritten by the new serial byte received.
This bit is cleared by the user; the new serial byte received is discarded.
7
SPIZEN
SPI transmit zeros when Tx FIFO is empty.
This bit is set to transmit 0x00 when there is no valid data in the Tx FIFO.
This bit is cleared to transmit the last transmitted value when there is no valid data in the Tx FIFO.
6
SPITMDE
SPI transfer and interrupt mode.
This bit is set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
This bit is cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
5
SPILF
LSB first transfer enable bit.
This bit is set by the user; the LSB is transmitted first.
This bit is cleared by the user; the MSB is transmitted first.
4
SPIWOM
SPI wired or mode enable bit.
This bit is set to 1 enable open-drain data output. External pull-ups are required on data out pins.
This bit is cleared for normal output levels.
3
SPICPO
Serial clock polarity mode bit.
This bit is set by the user; the serial clock idles high.
This bit is cleared by the user; the serial clock idles low.
2
SPICPH
Serial clock phase mode bit.
This bit is set by the user; the serial clock pulses at the beginning of each serial bit transfer.
This bit is cleared by the user; the serial clock pulses at the end of each serial bit transfer.
Rev. E
相關(guān)PDF資料
PDF描述
ATMEGA32L-8MUR MCU AVR 32K FLASH 8MHZ 44QFN
ATMEGA32-16MUR MCU AVR 32KB FLASH 16MHZ 44QFN
ADG528ATQ IC MULTIPLEXER 8X1 18CDIP
AD7511DIKNZ IC SWITCH QUAD SPST 16DIP
LX128V-5FN208C IC SWITCH DIGITAL 208FPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADUC7024 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
ADUC7024BCP62 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC &2X12-B DAC IC - Trays
ADUC7024BCP62-U1 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC &2X12-B DAC IC - Trays
ADUC7024BCPZ62 功能描述:IC MCU FLSH 62K ANLG I/O 64LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設(shè)備:電容感應(yīng)，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤
ADUC7024BCPZ62I 功能描述:IC MCU 12BIT 1MSPS ANLG 64LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*