參數(shù)資料
型號(hào)： ADUC7128BSTZ126
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 71/92頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
ADuC7128/ADuC7129
Rev. 0 | Page 73 of 92
Programmed Interrupts
As the programmed interrupts are nonmaskable, they are
controlled by the SWICFG register that writes into both the
IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG
registers at the same time. The 32-bit register dedicated to
software interrupt is SWICFG described in Table 106. This
MMR allows the control of programmed source interrupt.
Table 106. SWICFG MMR Bit Designations
Bit
Description
31:3
Reserved.
2
Programmed Interrupt (FIQ). Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed Interrupt (IRQ). Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, to be detected by the
interrupt controller and to be detected by the user in the
IRQSTA/FIQSTA register.
TIMERS
The ADuC7128/ADuC7129 have five general purpose
timers/counters.
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
The five timers in their normal mode of operation can be either
free-running or periodic.
In free-running mode, the counter decrements or increments
from the maximum or minimum value until zero scale or full
scale and starts again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero scale or full
scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero, if counting down; or full scale, if counting
up. An IRQ can be cleared by writing any value to clear the register
of the particular timer (TxICLR).
Table 107. Event Selection Numbers
ES
Interrupt Number
Name
00000
2
RTOS Timer (Timer0)
00001
3
GP Timer0 (Timer1)
00010
4
Wake-Up Timer (Timer2)
00011
5
Watchdog Timer (Timer3)
00100
6
GP Timer1 (Timer4)
00101
7
Flash Control 0
00110
8
Flash Control 1
00111
9
ADC Channel
01000
10
Quadrature Encoder
01001
11
I2C Slave0
01010
12
I2C Slave1
01011
13
I2C Master0
01100
14
I2C Master1
01101
15
SPI Slave
01110
16
SPI Master
01111
17
UART0
10000
18
UART1
10001
19
External IRQ0
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768. This gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and with a prescaler of 1.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD, which is loaded into the counter.
The current counter value can be read from T0VAL0. Timer0 has
a capture register (T0CAP) that can be triggered by a selected IRQ
source initial assertion. Once triggered, the current timer value is
copied to T0CAP, and the timer keeps running. This feature can be
used to determine the assertion of an event with more accuracy
than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0ICLR is written.
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