參數(shù)資料
型號(hào)： ADUC824BSZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/68頁
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤
REV. B
ADuC824
–31–
PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC824 incorporates two independent sigma-delta ADCs
(Primary and Auxiliary) with on-chip digital filtering intended
for the measurement of wide dynamic range, low frequency
signals, such as those in weigh-scale, strain-gauge, pressure trans-
ducer or temperature measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of 8 input ranges
from
±20 mV to ±2.56 V, being driven from one of three differ-
ential input channel options AIN1/2, AIN3/4, or AIN3/2. The
input channel is internally buffered allowing the part to handle
significant source impedances on the analog input, allowing R/C
filtering (for noise rejection or RFI reduction) to be placed on
SIGMA-DELTA
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
AGND
AV
DD
REFIN(–) REFIN(+)
PROGRAMMABLE GAIN
AMPLIFIER
THE PROGRAMMABLE
GAIN AMPLIFIER ALLOWS
EIGHT UNIPOLAR AND
EIGHT BIPOLAR INPUT
RANGES FROM 20mV TO
2.56V (EXT VREF = 2.5V)
THE MODULATOR PROVIDES
A HIGH-FREQUENCY 1-BIT
DATA STREAM (THE OUTPUT
OF WHICH IS ALSO CHOPPED)
TO THE DIGITAL FILTER,
THE DUTY CYCLE OF WHICH
REPRESENTS THE SAMPLED
ANALOG INPUT VOLTAGE
SIGMA-DELTA
MODULATOR
CHOP
ANALOG INPUT CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
CHOPPING YIELDS
EXCELLENT ADC OFFSET
AND OFFSET DRIFT
PERFORMANCE
OUTPUT AVERAGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA WORD OUTPUT
FROM THE FILTER IS
SUMMED AND AVERAGED
WITH ITS PREDECESSOR
TO NULL ADC CHANNEL
OFFSET ERRORS
AIN1
AIN2
AIN3
AIN4
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER
PRESENTS A HIGH
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUTS,
ALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES
BURNOUT CURRENTS
TWO 100nA BURNOUT
CURRENTS ALLOW THE
USER TO EASILY DETECT
IF A TRANSDUCER HAS
BURNED OUT OR GONE
OPEN-CIRCUIT
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE
VIA THE SF SFR
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED BY
THE CALIBRATION
COEFFICIENTS BEFORE
BEING PROVIDED AS
THE CONVERSION RESULT
OUTPUT SCALING
ANALOG MULTIPLEXER
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
FULLY DIFFERENTIAL PAIR OPTIONS AND
ADDITIONAL INTERNAL SHORT OPTION
(AIN2–AIN2).THE MULTIPLEXER IS
CONTROLLED VIA THE CHANNEL
SELECTION BITS IN ADC0CON
SIGMA-DELTA ADC
THE SIGMA-DELTA
ARCHITECTURE ENSURES
24 BITS NO MISSING
CODES. THE ENTIRE
SIGMA-DELTA ADC IS
CHOPPED TO REMOVE
DRIFT ERROR
OUTPUT
AVERAGE
OUTPUT
SCALING
DIGTAL OUTPUT
RESULT WRITTEN
TO ADC0H/M/L
SFRs
PGA
DIFFERENTIAL
REFERENCE
THE EXTERNAL REFERENCE
INPUT TO THE ADuC824 IS
DIFFERENTIAL AND
FACILITATES RATIOMETRIC
OPERATION. THE EXTERNAL
REFERENCE VOLTAGE IS
SELECTED VIA THE XREF0 BIT
IN ADC0CON.
REFERENCE DETECT
CIRCUITRY TESTS FOR OPEN OR
SHORTED REFERENCES INPUTS
CHOP
MUX
SEE PAGE 36
SEE PAGES 29 AND 34
SEE PAGE 34
SEE PAGE 35
SEE PAGE 36
SEE PAGE 37
SEE PAGE 35
SEE PAGE 33
SEE PAGES 27 AND 33
Figure 18. Primary ADC Block Diagram
the analog inputs if required. On-chip burnout currents can
also be turned on. These currents can be used to check that a
transducer on the selected channel is still operational before
attempting to take measurements.
The ADC employs a sigma-delta conversion technique to realize
up to 24 bits of no missing codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc3
programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion
result at programmable output rates from 5.35 Hz (186.77 ms)
to 105.03 Hz (9.52 ms). A Chopping scheme is also employed
to minimize ADC offset errors. A block diagram of the Primary
ADC is shown in Figure 18.
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