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| 型號(hào)： | ADUC824BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 66/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
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REV. B
–7–
ADuC824
Parameter
ADuC824BS
Test Conditions/Comments
Unit
POWER REQUIREMENTS (continued)
Power Supply Currents Normal Mode
17, 18
DVDD Current
4
DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz
mA max
2.1
DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz
mA max
AVDD Current
170
AVDD = 5.25 V, Core CLK = 1.57 MHz
A max
DVDD Current
15
DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz
mA max
8DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz
mA max
AVDD Current
170
AVDD = 5.25 V, Core CLK = 12.58 MHz
A max
Power Supply Currents Idle Mode
17, 18
DVDD Current
1.2
DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz
mA max
750
DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz
A typ
AVDD Current
140
Measured @ AVDD = 5.25 V, Core CLK = 1.57 MHz
A typ
DVDD Current
2
DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz
mA typ
1DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz
mA typ
AVDD Current
140
Measured at AVDD = 5.25 V, Core CLK = 12.58 MHz
A typ
Power Supply Currents Power-Down Mode
17, 18
Core CLK = 1.57 MHz or 12.58 MHz
DVDD Current
50
DVDD = 4.75 V to 5.25 V, Osc. On, TIC On
A max
20
DVDD = 2.7 V to 3.6 V, Osc. On, TIC On
A max
AVDD Current
1
Measured at AVDD = 5.25 V, Osc. On or Osc. Off
A max
DVDD Current
20
DVDD = 4.75 V to 5.25 V, Osc. Off
A max
5DVDD = 2.7 V to 3.6 V, Osc. Off
A typ
Typical Additional Power Supply Currents
Core CLK = 1.57 MHz, AVDD = DVDD = 5 V
(AIDD and DIDD)
PSM Peripheral
50
A typ
Primary ADC
1
mA typ
Auxiliary ADC
500
A typ
DAC
150
A typ
Dual Current Sources
400
A typ
NOTES
1 Temperature Range: –40
°C to +85°C.
2 These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
3 System Zero-Scale Calibration can remove this error.
4 The primary ADC is factory calibrated at 25
°C with AV
DD = DVDD = 5 V yielding this full-scale error of 10
V. If user power supply or temperature conditions are
significantly different than these, an Internal Full-Scale Calibration will restore this error to 10
V. A system zero-scale and full-scale calibration will remove this
error altogether.
5 Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6 The auxiliary ADC is factory calibrated at 25
°C with AV
DD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.
7 DAC linearity and AC Specifications are calculated using:
reduced code range of 48 to 4095, 0 to VREF,
reduced code range of 48 to 3995, 0 to VDD.
8 Gain Error is a measure of the span error of the DAC.
9 In general terms, the bipolar input voltage range to the primary ADC is given by Range
ADC =
±(V
REF 2
RN)/125, where:
VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., VREF = 2.5 V
and RN2, RN1, RN0 = 1, 1, 0 the RangeADC =
±1.28 V. In unipolar mode the effective range is 0 V to 1.28 V in our example.
10 1.25 V is used as the reference voltage to the ADC when internal V
REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.
11 In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A
GND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar
range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV.
12 Pins configured in I2C-compatible mode or SPI mode, pins configured as digital inputs during this test.
13 Pins configured in I2C-compatible mode only.
14 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
15 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40
°C, +25°C and +85°C; typical endurance at 25°C is 700 K cycles.
16 Retention lifetime equivalent at junction temperature (T
J) = 55
°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6e V
will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.
17 Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in
PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR.
18 DV
DD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
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