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參數(shù)資料
| 型號： | ADUC831BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52-MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
–48–
ADuC831
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 39) and,
in that state, they can be used as inputs. As inputs, Port 2 pins
being pulled externally low will source current because of the
internal pull-up resistors. Port 2 pins with 0s written to them
will drive a logic low output voltage (VOL) and will be capable of
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. In the case that
they are selected as the PWM outputs via the CFG831 SFR, the
PWM outputs will overwrite anything written to P2.6 or P2.7.
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
ADDR
P2.x
PIN
DVDD
INTERNAL
PULL-UP*
*SEE FIGURE 39 FOR
DETAILS OF INTERNAL PULL-UP
Figure 38. Port 2 Bit Latch and I/O Buffer
Q
FROM
PORT
LATCH
2 CLK
DELAY
Q1
DVDD
Q2
DVDD
Q3
DVDD
Px.x
PIN
Q4
Figure 39. Internal Pull-Up Configuration
Port 3
Port 3 is a bidirectional port with internal pull-ups directly con-
trolled via the P3 SFR. Port 3 pins that have 1s written to them
are pulled high by the internal pull-ups, and in that state, can be
used as inputs. As inputs, Port 3 pins being pulled externally low
will source current because of the internal pull-ups. Port 3 pins
with 0s written to them will drive a logic low output voltage (VOL)
and will be capable of sinking 4 mA.
Port 3 pins also have various secondary functions described in
Table XVIII. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table XVIII. Port 3, Alternate Pin Functions
Pin
Alternate Function
P3.0
RxD (UART Input Pin) (or Serial Data I/O in Mode 0)
P3.1
TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
P3.2
INT0 (External Interrupt 0)
P3.3
INT1 (External Interrupt 1)/PWM 1/MISO
P3.4
T0 (Timer/Counter 0 External Input)
PWM External Clock/PWM 0
P3.5
T1 (Timer/Counter 1 External Input)
P3.6
WR (External Data Memory Write Strobe)
P3.7
RD (External Data Memory Read Strobe)
P3.4 and P2.3 can also be used as PWM outputs. In the case that
they are selected as the PWM outputs via the CFG831 SFR, the
PWM outputs will overwrite anything written to P3.4 or P3.3.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
P3.x
PIN
INTERNAL
PULL-UP*
*SEE FIGURE 39
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Figure 40. Port 3 Bit Latch and I/O Buffer
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I
2C pins
(SCLOCK and SDATA/MOSI) also feature both input and
output functions. Their equivalent I/O architectures are illus-
trated in Figure 41 and Figure 43, respectively, for SPI
operation and in Figure 42 and Figure 44 for I
2C operation.
Notice that in I
2C mode (SPE = 0) the strong pull-up FET
(Q1) is disabled, leaving only a weak pull-up (Q2) present. By
contrast, in SPI mode (SPE = 1) the strong pull-up FET (Q1)
is controlled directly by SPI hardware, giving the pin push/pull
capability.
In I
2C mode (SPE = 0) two pull-down FETs (Q3 and Q4)
operate in parallel in order to provide an extra 60% or 70% of
current sinking capability. In SPI mode (SPE = 1), however,
only one of the pull-down FETs (Q3) operates on each pin
resulting in sink capabilities identical to that of Port 0 and
Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I
2C hard-
ware, a filter conditions the signals in order to reject glitches of
up to 50 ns in duration.
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I2C master mode.
Therefore, if you are not using the SPI or I2C functions, you can
use these two pins to give additional high current digital outputs.
HARDWARE SPI
(MASTER/SLAVE)
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
DVDD
SCLOCK
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 41. SCLOCK Pin I/O Functional Equivalent
in SPI Mode
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