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REV. 0
–6–
ADuC831
NOTES
1Temperature Range –40C to +125C.
2ADC linearity is guaranteed during normal Micro Converter core operation.
3ADC LSB Size = V
REF/2
12 i.e., for Internal V
REF = 2.5 V, 1 LSB = 610
V and for External VREF =1 V, 1 LSB = 244 V.
4These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
5Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
6Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve
these specifications.
7SNR calculation includes distortion and noise components.
8Channel-to-channel Crosstalk is measured on adjacent channels.
9The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.
10DAC linearity is calculated using:
Reduced code range of 100 to 4095, 0 to VREF range.
Reduced code range of 100 to 3945, 0 to VDD range.
DAC Output Load = 10 k
and 100 pF.
11DAC differential nonlinearity specified on 0 to V
REF and 0 to VDD ranges
12DAC specification for output impedance in the unbuffered case depends on DAC code.
13DAC specifications for I
SINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC
in unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14Measured with V
REF and CREF pins decoupled with 0.1
F capacitors to ground. Power-up time for the internal reference will be determined by the value of the
decoupling capacitor chosen for both the VREF and CREF pins.
15When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode the V
REF and CREF
pins need to be shorted together for correct operation.
16Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40C, +25C, and +125C. Typical endurance at
25C is 700,000 cycles.
18Retention lifetime equivalent at junction temperature (Tj) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section of this data sheet.
19Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Executing internal software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O pins and Port 1 are open circuit, OSC off, TIC off.
20DV
DD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
Parameter
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
POWER REQUIREMENTS
19, 20
Power Supply Voltages
AVDD/DVDD to AGND
2.7
V min
AVDD /DVDD = 3 V nom
3.3
V max
4.5
V min
AVDD /DVDD = 5 V nom
5.5
V max
Power Supply Currents Normal Mode
DVDD Current
6
3
mA typ
MCLKIN = 1 MHz
AVDD Current
1.7
mA max
MCLKIN = 1 MHz
DVDD Current
25
12
mA max
MCLKIN = 16 MHz
21
10
mA typ
MCLKIN = 16 MHz
AVDD Current
1.7
mA max
MCLKIN = 16 MHz
Power Supply Currents Idle Mode
DVDD Current
5
1
mA typ
MCLKIN = 1 MHz
AVDD Current
0.14
mA typ
MCLKIN = 1 MHz
DVDD Current
4
11
5
mA max
MCLKIN = 16 MHz
10
4
mA typ
MCLKIN = 16 MHz
AVDD Current
0.14
mA typ
MCLKIN = 16 MHz
Power Supply Currents Power Down Mode
MCLKIN = 2 MHz or 16 MHz
AVDD Current
3
2.5
A typ
DVDD Current
35
20
A max
TIMECON.1 = 0
25
12
A typ
160
125
A typ
TIMECON.1 = 1
Typical Additional Power Supply Currents
AVDD = DVDD = 5 V
PSM Peripheral
50
A typ
ADC
1.5
mA typ
DAC
150
A typ
SPECIFICATIONS (continued)